C
Christian Landrault
Researcher at University of Montpellier
Publications - 105
Citations - 1985
Christian Landrault is an academic researcher from University of Montpellier. The author has contributed to research in topics: Automatic test pattern generation & Fault coverage. The author has an hindex of 23, co-authored 105 publications receiving 1959 citations.
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Proceedings ArticleDOI
A modified clock scheme for a low power BIST test pattern generator
Patrick Girard,L. Guiller,Christian Landrault,Serge Pravossoudovitch,Hans-Joachim Wunderlich +4 more
TL;DR: A new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation and numerous advantages can be found in applying such a technique during BIST.
Proceedings ArticleDOI
A gated clock scheme for low power scan testing of logic ICs or embedded cores
TL;DR: A novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores is presented, based on a gated clock scheme for the scan path and the clock tree feeding thescan path.
Proceedings ArticleDOI
Reducing power consumption during test application by test vector ordering
TL;DR: The proposed approach is based on a re-ordering of the vectors in the test sequence to minimize the switching activity of the circuit during test application and guarantees a decrease in power consumption and heat dissipation.
Proceedings ArticleDOI
Power driven chaining of flip-flops in scan architectures
TL;DR: A novel approach for scan cell ordering which significantly reduces the power consumed during scan testing is presented, based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing.
Proceedings ArticleDOI
Efficient scan chain design for power minimization during scan testing under routing constraint
TL;DR: A new technique is presented that allows to design power-optimized scan chains under a given routing constraint based on clustering and reordering of scan cells in the design and allows to reduce average power consumption during scan testing.