There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

/pdf/statistical-theory-of-communication-4wy4yg9ato.pdf

Statistical Theory of Communication

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Introduction. UWB Channel Models. Modulation Schemes. Receiver Structures. Integrated Circuit Topologies. UWB Antennas. Medium Access Control. Positioning.

UWB theory and applications

Partial table of contents: Integrated--Circuit Devices and Modelling. Processing and Layout. Basic Current Mirrors and Single--Stage Amplifiers. Noise Analysis and Modelling. Basic Opamp Design and Compensation. Advanced Current Mirrors and Opamps. Comparators. Switched--Capacitor Circuits. Nyquist--Rate D/A Converters. Oversampling Converters. Phase--Locked Loops. Index.

/pdf/analog-integrated-circuit-design-magtnc6enj.pdf

Analog Integrated Circuit Design

In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary /spl Delta//spl Sigma/ topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and DC offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved /spl Delta//spl Sigma/ analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented.

/pdf/time-interleaved-oversampling-a-d-converters-theory-and-249k8qugxv.pdf

Time-interleaved oversampling A/D converters: theory and practice

Analog integrated circuit design. 2nd ed.

It is well known that DC offsets degrade the performance of analog adaptive filters. In this paper, the effects of DC offsets on four variations of the stochastic gradient algorithm are analyzed. Assuming a Gaussian probability distribution for the input signal and error signal, the output mean squared error (MSE) performance in the presence of DC offsets is evaluated for each of the algorithms. The theoretical work is compared with computer simulations and the results, together with convergence properties of each of the algorithms and their respective hardware requirements, are used in selecting the most appropriate algorithm. Although a Gaussian input distribution is assumed, it may reasonably be inferred that the critical results obtained should also hold for other input distributions. >

Comparison of DC offset effects in four LMS adaptive algorithms

This paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels. To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-Ethernet. Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 24 wire hybrids, echo cancellation, digital equalization, and clock recovery. Typical integrated circuit approaches for realizing each of these blocks are presented as well as possible tradeoffs. Finally, future challenges facing integrated circuit designers are presented.

David A. Johns

Papers

Analog Integrated Circuit Design

Time-interleaved oversampling A/D converters: theory and practice

Analog integrated circuit design. 2nd ed.

Comparison of DC offset effects in four LMS adaptive algorithms

Integrated circuits for data transmission over twisted-pair channels