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David M. Binkley
Researcher at University of North Carolina at Charlotte
Publications - 50
Citations - 2046
David M. Binkley is an academic researcher from University of North Carolina at Charlotte. The author has contributed to research in topics: CMOS & Flicker noise. The author has an hindex of 21, co-authored 50 publications receiving 1978 citations. Previous affiliations of David M. Binkley include North Carolina State University & University of California, Los Angeles.
Papers
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Journal ArticleDOI
MicroPET: a high resolution PET scanner for imaging small animals
Simon R. Cherry,Yiping Shao,Robert W. Silverman,K. Meadors,Stefan Siegel,Arion F. Chatziioannou,J. Young,J. Young,W. Jones,J.C. Moyers,D.F. Newport,A. Boutefnouchet,T.H. Farquhar,Mark S. Andreaco,Mark S. Andreaco,M. Paulus,David M. Binkley,R. Nutt,Michael E. Phelps +18 more
TL;DR: MicroPET as discussed by the authors is the first PET scanner to incorporate the new scintillator LSO and to our knowledge is the highest resolution multi-ring PET scanner currently in existence, which consists of a ring of 30 position sensitive scintillation detectors, each with an 8/spl times/8 array of small lutetium oxyorthosilicate (LSO) crystals coupled via optical fibers to a multi-channel photomultiplier tube.
Book
Tradeoffs and Optimization in Analog CMOS Design
TL;DR: In this paper, the authors present hand expressions motivated by the EKV MOS model and measured data for MOS device performance, including velocity saturation and other small-geometry effects.
Journal ArticleDOI
A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications
B.K. Swann,Benjamin J. Blalock,L.G. Clonts,David M. Binkley,J.M. Rochelle,E. Breeding,K.M. Baldwin +6 more
TL;DR: The design is believed to be the first fully integrated CMOS subnanosecond time-to-digital TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.
Journal ArticleDOI
A CAD methodology for optimizing transistor current and sizing in analog CMOS design
TL;DR: A computer-aided design methodology for optimizing MOS transistor current and sizing is presented where drain current ID, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized selection of channel width for layout.
Journal ArticleDOI
A miniaturized neuroprosthesis suitable for implantation into the brain
M. Mojarradi,David M. Binkley,Benjamin J. Blalock,Richard A. Andersen,N. Ulshoefer,T. Johnson,L. Del Castillo +6 more
TL;DR: This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring.