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Journal ArticleDOI

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

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TLDR
The design is believed to be the first fully integrated CMOS subnanosecond time-to-digital TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.
Abstract
An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

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Citations
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Journal ArticleDOI

A CMOS time-to-digital converter with better than 10 ps single-shot precision

TL;DR: A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.
Journal ArticleDOI

A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

TL;DR: A high-resolution time-to-digital converter implemented in a general purpose field-programmable-gate-array (FPGA) is presented and dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement.
Journal ArticleDOI

A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology

TL;DR: The target application for this sensor is time-resolved imaging, in particular fluorescence lifetime imaging microscopy and 3D imaging, and the characterization shows the suitability of the proposed sensor technology for these applications.
Journal ArticleDOI

A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

TL;DR: This paper presents a short review of time-to-digital and digital- to-time converters (TDCs and DTCs) adopting a time-mode signal-processing perspective, and the primary definitions, operating principles, and basic building blocks are presented.
Journal ArticleDOI

A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation

TL;DR: A time-to-digital converter architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel with a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity.
References
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Book

CMOS Circuit Design, Layout, and Simulation

TL;DR: Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.
Journal ArticleDOI

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

TL;DR: Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.
Journal ArticleDOI

Design techniques for high-speed, high-resolution comparators

TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
Journal ArticleDOI

Full-speed testing of A/D converters

TL;DR: Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described.
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Positron emission tomography and autoradiography: Principles and applications for the brain and heart

TL;DR: This is a text on cerebral and myocardial imaging using positron emission tomography and autoradiography using positrons emission tomographic and tracer kinetic models.
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