D
Dinesh K. Sharma
Researcher at Indian Institute of Technology Bombay
Publications - 153
Citations - 1871
Dinesh K. Sharma is an academic researcher from Indian Institute of Technology Bombay. The author has contributed to research in topics: CMOS & Voltage. The author has an hindex of 22, co-authored 150 publications receiving 1611 citations. Previous affiliations of Dinesh K. Sharma include Indian Institutes of Technology & Tata Institute of Fundamental Research.
Papers
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Proceedings Article
Resolution enhancement techniques for optical lithography
TL;DR: The development of simulation programs which help to determine the effectiveness of resolution enhancement techniques in achieving a given resolution at a specified wavelength are described.
Journal ArticleDOI
Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization
TL;DR: In this paper, the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions was studied and the use of high-kappa spacers to enhance the effect of GFIBL and thereby achieve better device and circuit performance.
Journal ArticleDOI
Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures
Mayank Shrivastava,M. Agrawal,S. Mahajan,Harald Gossner,T. Schulz,Dinesh K. Sharma,Valipe Ramgopal Rao +6 more
TL;DR: In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.
Proceedings ArticleDOI
Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
Angada B. Sachid,Roswald Francis,Maryam Shojaei Baghini,Dinesh K. Sharma,K.-H. Bach,R. Mahnkopf,Valipe Ramgopal Rao +6 more
TL;DR: In this paper, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped finFET.
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Macroporous silicon based capacitive affinity sensor—fabrication and electrochemical studies
TL;DR: In this article, the authors report the fabrication and characterization of capacitive immunosensors based on electrolyte-insulator-porous silicon (EIS) structures, which are found to be five times more sensitive than an immunosensor on polished silicon with identical die area.