There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.

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Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems

1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Today, the price of building a factory to produce submicron size electronic devices on 300 mm Si wafers is over billions of dollars. In processing a 300 mm Si wafer, over half of the production cost comes from fabricating the very-large-scale-integration of the interconnect metallization. The most serious and persistent reliability problem in interconnect metallization is electromigration. In the past 40 years, the microelectronic industry has used Al as the on-chip conductor. Due to miniaturization, however, a better conductor is needed in terms of resistance–capacitance delay, electromigration resistance, and cost of production. The industry has turned to Cu as the on-chip conductor, so the question of electromigration in Cu metallization must be examined. On the basis of what we have learned from the use of Al in devices, we review here what is current with respect to electromigration in Cu. In addition, the system of interconnects on an advanced device includes flip chip solder joints, which now tend ...

Recent advances on electromigration in very-large-scale-integration of interconnects

Electromigration-induced stress distributions in 200 μm long, 10 μm wide aluminum conductor lines in 1.5 μm SiO2 passivation layers have been investigated in real time using synchrotron-based white-beam x-ray microdiffraction. The results show that a steady-state linear stress gradient along the length of the line developed within the first few hours of electromigration and that the stress gradient could be manipulated by controlling the magnitude and the direction of the current flow. From the current density dependence of the steady-state stress gradient, the effective valence Z* was determined to be 1.6 at 260 °C. From the time dependence of the transient-state stress gradient, the effective grain boundary diffusion coefficient Deff was estimated to be 8.2×10−11 cm2/s at 260 °C using Korhonen’s stress evolution model [M. A. Korhonen, P. Bo/rgesen, K. N. Tu, and C.-Y. Li, J. Appl. Phys. 73, 3790 (1993)]. Both Z* and Deff values are in good agreement with the previously reported values.

Electromigration-induced stress in aluminum conductor lines measured by x-ray microdiffraction

The electromigration threshold in copper interconnects is reported in this study. The length-dependent electromigration degradation rate is observed and quantified in the temperature range of 295–400 °C. Based on the Blech electromigration model [I. A. Blech, J. Appl. Phys. 47, 1203 (1976)], a simplified equation is proposed to analyze the experimental data from various combinations of current density and interconnect length, as well as to estimate the electromigration threshold product of current density and line length, (jL)th, at a certain temperature. The resulting (jL)th value appears to be temperature dependent, decreasing with increasing temperature in the tested range between 295 and 400 °C.

Electromigration threshold in copper interconnects

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

Foundation of rf CMOS and SiGe BiCMOS technologies

The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

Process of enclosing via for improved reliability in dual damascene interconnects

Barrier property, gap-fill quality, and electromigration (EM) resistance of a TaN diffusion barrier with ultrathin-Cu/Ru(Ta) liner layers were carried out to evaluate its feasibility for back-end-of-the-line Cu/low- k interconnects. Ru/TaN and Ru0.9 Ta0.1/TaN liner stacks show comparable oxidation and Cu diffusion barrier properties to the conventional Ta/TaN bilayer liner stack. Through observed better wettability to ultrathin Cu seed and therefore enhanced gap-fill quality, both Ru/TaN and Ru0.9 Ta0.1/TaN liner stacks show EM resistance improvement over the Ta/TaN bilayer liner system.

Ping-Chuan Wang

Papers

Electromigration-induced stress in aluminum conductor lines measured by x-ray microdiffraction

Electromigration threshold in copper interconnects

Foundation of rf CMOS and SiGe BiCMOS technologies

Process of enclosing via for improved reliability in dual damascene interconnects

Characterization of “Ultrathin-Cu”/Ru(Ta)/TaN Liner Stack for Copper Interconnects