Eric Beyne

TL;DR: Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3- D SoCs at low area and power and digital gates can directly drive signals through TSVs at high speed and low power.

TL;DR: In this article, a method of fabricating a microstructure having an inside cavity is described, which includes depositing a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate and then aligning and bonding the first substrate on a second substrate such that a micro structure having a cavity is formed according to the closed geometry configuration.

TL;DR: In this article, the progress in RF-MEMS from a device and integration perspective is reviewed, and the worldwide state-of-the-art of RFMEMS devices including switches, variable capacitors, resonators and filters are described.

TL;DR: Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the authors demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm.

TL;DR: In this paper, a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of attaching one of the major surfaces of the first substrate to a carrier by means of a release layer, and attaching the other major surface of the one substrate to the second substrate with a curable polymer adhesive layer, was presented.