F
F. Andrieu
Researcher at French Alternative Energies and Atomic Energy Commission
Publications - 10
Citations - 241
F. Andrieu is an academic researcher from French Alternative Energies and Atomic Energy Commission. The author has contributed to research in topics: Silicon on insulator & Electron mobility. The author has an hindex of 4, co-authored 10 publications receiving 221 citations.
Papers
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Journal ArticleDOI
Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
J-P Noel,Olivier Thomas,M.-A. Jaud,Olivier Weber,Thierry Poiroux,C. Fenouillet-Beranger,P. Rivallin,P. Scheiblin,F. Andrieu,M. Vinet,O. Rozeau,Frederic Boeuf,O. Faynot,Amara Amara +13 more
TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Proceedings ArticleDOI
32nm and beyond Multi-V T Ultra-Thin Body and BOX FDSOI: From device to circuit
Olivier P. Thomas,J.-P. Noel,C. Fenouillet-Beranger,M.-A. Jaud,J. Dura,P. Perreau,Frederic Boeuf,F. Andrieu,Daniel Delprat,F. Boedt,Konstantin Bourdelle,Bich-Yen Nguyen,Andrei Vladimirescu,A. Amara +13 more
TL;DR: A low-cost and high-manufacturability Multi-VT Ultra-Thin BOX and Body (UT2B) FDSOI technology is proposed for high-performance and low-leakage digital circuits.
Journal ArticleDOI
Evidences on the Physical Origin of the Unexpected Transport Degradation in Ultimate n-FDSOI Devices
V. Barral,Thierry Poiroux,S. Barraud,F. Andrieu,O. Faynot,Daniela Munteanu,J.L. Autran,S. Deleonibus +7 more
TL;DR: In this paper, experimental carrier mean-free-paths have been determined on strained and unstrained fully depleted silicon-on-insulator (n-FDSOI) devices with Si film thickness ranging from 11.8 to 2.5 nm, gate length down to 30 nm.
Book ChapterDOI
Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond
T. Poiroux,F. Andrieu,O. Weber,C. Fenouillet-Béranger,C. Buj-Dufournet,P. Perreau,L. Tosti,L. Brevard,O. Faynot +8 more
TL;DR: In this paper, the use of an ultrathin buried oxide together with an implanted backplane brings additional flexibility in terms of threshold voltage adjustment and ensures the efficiency of conventional power management techniques based on back-biasing, even in very aggressively scaled devices.
Proceedings ArticleDOI
Electron mean-free-path experimental extraction on ultra-thin and ultra-short strained and unstrained FDSOI n-MOSFETs
V. Barral,Thierry Poiroux,S. Barraud,O. Bonno,F. Andrieu,C. Buj-Dufournet,L. Brevard,D. Lafond,Olivier Faynot,Daniela Munteanu,J.L. Autran,Simon Deleonibus +11 more
TL;DR: In this paper, a quasi-ballistic extraction methodology dedicated to low longitudinal field conditions was used to determine carrier mean-tree-paths on both strained and unstrained n-FDSOI devices with Si film thickness down to 2.5 nm and a TiN/HfO2 gate stack.