O
O. Rozeau
Researcher at French Alternative Energies and Atomic Energy Commission
Publications - 45
Citations - 1718
O. Rozeau is an academic researcher from French Alternative Energies and Atomic Energy Commission. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 19, co-authored 43 publications receiving 1541 citations.
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Proceedings ArticleDOI
28nm FDSOI technology platform for high-speed low-voltage digital applications
Nicolas Planes,Olivier Weber,V. Barral,Sebastien Haendler,D. Noblet,D. Croain,M. Bocat,P.O. Sassoulas,Xavier Federspiel,Antoine Cros,A. Bajolet,E. Richard,B. Dumont,Pierre Perreau,David Petit,Dominique Golanski,Claire Fenouillet-Beranger,N. Guillot,Mustapha Rafik,Vincent Huard,S. Puget,X. Montagner,M-A. Jaud,O. Rozeau,O. Saxod,Francois Wacquant,Frederic Monsieur,D. Barge,L. Pinzelli,M. Mellier,Frederic Boeuf,Franck Arnaud,Michel Haond +32 more
TL;DR: This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology, to show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values.
Journal ArticleDOI
Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
J-P Noel,Olivier Thomas,M.-A. Jaud,Olivier Weber,Thierry Poiroux,C. Fenouillet-Beranger,P. Rivallin,P. Scheiblin,F. Andrieu,M. Vinet,O. Rozeau,Frederic Boeuf,O. Faynot,Amara Amara +13 more
TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Proceedings ArticleDOI
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot,Francois Andrieu,Olivier Weber,Claire Fenouillet-Beranger,Pierre Perreau,J. Mazurier,T. Benoist,O. Rozeau,Thierry Poiroux,Maud Vinet,Laurent Grenouillet,J.-P. Noel,Nicolas Posseme,Sébastien Barnola,François Martin,C. Lapeyre,Mikael Casse,X. Garros,M-A. Jaud,Olivier P. Thomas,G. Cibrario,L. Tosti,L. Brevard,Claude Tabone,P. Gaud,Sylvain Barraud,Thomas Ernst,Simon Deleonibus +27 more
TL;DR: In this article, the main advantages of planar undoped channel Fully depleted SOI devices are discussed and solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are reported.
Proceedings ArticleDOI
3DVLSI with CoolCube process: An alternative path to scaling
Perrine Batude,Claire Fenouillet-Beranger,L. Pasini,V. Lu,F. Deprat,Laurent Brunet,Benoit Sklenard,F. Piegas-Luce,M. Casse,B. Mathieu,O. Billoint,G. Cibrario,Ogun Turkyilmaz,Hossam Sarhan,Sebastien Thuries,Louis Hutin,S. Sollier,Julie Widiez,L. Hortemel,Claude Tabone,M.-P. Samson,Bernard Previtali,N. Rambal,F. Ponthenier,J. Mazurier,Remi Beneyton,M. Bidaud,Emmanuel Josse,E. Petitprez,O. Rozeau,Maurice Rivoire,C. Euvard-Colnat,A. Seignard,F. Fournel,L. Benaissa,Perceval Coudrain,P. Leduc,J.M. Hartmann,Pascal Besson,Sebastien Kerdiles,C. Bout,Fabrice Nemouchi,A. Royer,C. Agraffeil,G. Ghibaudo,Thomas Signamarcheix,Michel Haond,Fabien Clermidy,O. Faynot,Maud Vinet +49 more
TL;DR: In this paper, the authors propose a 3D VLSI with a CoolCube integration to vertically stack several layers of devices with a unique connecting via density above a million/mm2.
Proceedings ArticleDOI
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
Francois Andrieu,Olivier Weber,J. Mazurier,Olivier P. Thomas,J.-P. Noel,Claire Fenouillet-Beranger,J-P. Mazellier,Pierre Perreau,Thierry Poiroux,Yves Morand,T. Morel,S. Allegret,Virginie Loup,Sébastien Barnola,François Martin,J.-F. Damlencourt,I. Servin,M. Casse,X. Garros,O. Rozeau,M-A. Jaud,G. Cibrario,J. Cluzel,Alain Toffoli,F. Allain,R. Kies,D. Lafond,Vincent Delaye,Claude Tabone,L. Tosti,L. Brevard,P. Gaud,Vamsi Paruchuri,Konstantin Bourdelle,Walter Schwarzenbach,O. Bonnin,By. Nguyen,Bruce B. Doris,Frederic Boeuf,Thomas Skotnicki,O. Faynot +40 more
TL;DR: In this paper, the authors used a single mid-gap gate stack to produce 6T-SRAM cells with good characteristics down to V DD = 0.5V supply voltage and with excellent SNM dispersion across the wafer.