Showing papers by "Fabrizio Lombardi published in 2010"

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

Abstract: This paper proposes a new design of a highly stable and low-power static RAM (SRAM) cell using carbon nanotube FETs (CNTFETs) that utilizes different threshold voltages for best performance. In a CNT, the threshold voltage can be adjusted by controlling the chirality vector (i.e., the diameter). In the proposed six-transistor SRAM cell design, while all CNTFETs of the same type have the same chirality, n-type and p-type transistors have different chiralities, i.e., a dual-diameter design of SRAM cell. As figures of merit, stability, power dissipation, and write time are considered when selecting the chirality for the best overall performance. A new metric, denoted as ?SPR,? is proposed to capture these figures of merit. This metric shows that a CNTFET-based SRAM cell provides an ?SPR? that is four times higher than for its CMOS counterpart that has the same configuration, thus attaining superior performance. Finally, the sensitivity of the CNTFET SRAM design to process variations is assessed and compared with its CMOS design counterpart. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based SRAM cell due to variations in the diameter, supply voltage, and temperature of the CNTFETs. The CNTFET-based SRAM cell demonstrates that it tolerates the process, power supply voltage, and temperature variations significantly better than its CMOS counterpart.

An information-theoretic analysis of quantum-dot cellular automata for defect tolerance

Abstract: Quantum-dot cellular automata (QCA) has been advocated as a promising emerging nanotechnology for designing future nanocomputing systems. However, at device level, the large number of expected defects represents a significant hurdle for reliable computation in QCA-based systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect tolerance and redundancy in QCA devices. By modeling defect-prone QCA devices as unreliable information processing media, we determine the information transfer capacity, as bound on the reliability that QCA devices can achieve. The proposed method allows to evaluate the effectiveness of redundancy-based defect tolerance in an effective and quantitative manner.

Modelling and extracting parameters of organic solar cells

Abstract: A model that captures the physical phenomena behind the operation of organic solar cells is proposed. This model is simple and suitable for parameter extraction. By simulation, it is shown that the I-V characteristics of the single diode model, the double diode model and the proposed model are in good agreement and close to experimental values. An extraction method is proposed and validated by fitting simulated and experimental results.

High throughput and low power dissipation in QCA pipelines using Bennett clocking

Abstract: This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

Modelling a CNTFET with Undeposited CNT Defects

Abstract: The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. When designing and manufacturing a CNTFET, additional features such as pitch, number and position of the CNTs must be considered to assess its performance. One of the defect types that can occur when fabricating a CNTFET, is the absence of some CNTs following the deposition/growth step. As result of this type of defect, a CNTFET will show a change in operational characteristics because drain current, gate capacitance, and delay will be affected due to the lower number of CNTs present in the channel of the transistor. This paper presents a new model by which the drain current, the gate capacitance and the delay can be found when not all CNTs are deposited on the substrate. This results in an uneven CNT spacing, new equations are derived and shown to be applicable to both defective and defect-free CNTFETs. The proposed model has been implemented in MATLAB and has been extensively simulated to show that defects due to undeposited CNTs have a significant impact on the operation of a CNTFET. Degradation in performance is related to both the number and position of the defects.

Time/Temperature Degradation of Solar Cells under the Single Diode Model

Abstract: This paper presents an extensive analysis of the degradation of solar cells due to time and temperature. This analysis is based on the single diode model (SDM) and relies on HSPICE to initially establish through simulation the relationships between model parameters, efficiency and process variations. The analysis is extended to the operational temperature and time by extracting the degradation in the performance of the solar cell. The result shows that the efficiency of solar cells has an inverse relationship with temperature (i.e. at high temperature the efficiency degrades), irradiance levels are affected by the change of the photo-generation current and the series resistance in the single diode model. Moreover, when time is considered (at a fixed temperature), the resulting degradation is analyzed by extraction and optimization of the SDM parameters, in this case, every parameter decreases linearly except the diode saturation current and the diode ideality factor that increase by polynomial and linear relationships, respectively.

Double diode modeling of time/temperature induced degradation of solar cells

Abstract: This paper presents a simulation-based analysis of degradation of a solar cell as induced by temperature and/or time. Based on the double diode model (DDM) and using HSPICE, relationships are found between the parameters of the equivalent electrical circuit and efficiency, process variations and optimization in its operation. The results of this paper show that time, temperature and irradiance are of significance in DDM, because they affect the efficiency of a solar cell when degradation occurs.

Read-out schemes for a CNTFET-based crossbar memory

Abstract: This paper investigates read-out schemes for a crossbar memory using CNTFET-based elements as cross-points. Two read-out schemes are presented in this paper; the first scheme biases the selected junction and measures the current flowing from the junction toward the ground while the second scheme involves biasing all other unselected bits and/or wordlines. Two figures of merit (the sense voltage on/off ratio and the sense current noise margin) are used to investigate the effectiveness of the proposed schemes for the CNTFET-based crossbar memory. Simulation results show that the CNTFET-based crossbar memory achieves improvements in both sense voltages on/off ratio and noise margin compared to the molecular memory implementation. Therefore, this paper demonstrates that these schemes make the CNTFET-based design a viable candidate for crossbar memory in the nanoscale era.

Modeling Open Defects in Nanometric Scale CMOS

Abstract: Open defects are extremely common in CMOS circuits. They can either be a partial or complete breaking of an input line. The complete breaking of the line is referred to as strong or full open defect. Until few years ago, a full open defect on any interconnecting line has been considered as floating. In nanometric CMOS technology, in which gate leakage currents are not negligible, full open defect lines cannot be considered to be electrically isolated. The final value of the node is independent of the initial state of the node and totally depends on the topological characteristics of the gate. Experimental evidence of the behavior of all basic gates at 90nm, 64nm and 32nm is provided, this shows a decrease in the drain current to gate leakage current ratio, in the technology scaling. The effect of full opens at the gates has also been tested by varying the PVT conditions. These variations provide a range of variation for the full open input voltage and gate leakage current. The effect of full opens on various circuits like the full adder has also been documented at various nanometric levels.

Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates

Abstract: DNA self-assembly has been proposed as a promising "bottomup" manufacturing technique to supersede photolithography at nanometer scale. This paper discusses the application of DNA self-assembly for manufacturing templates of QCA circuits. Using a synthesis algorithm, a tile set of reduced cardinality is utilized for growing multiple patterns of the same QCA circuit on a two-dimensional template. Errors in the DNA self-assembly process are then considered; their implications on the operation of faulty QCA circuits following the deposition of QCA cells, are discussed. The errors are mostly clustered and along facets; a detailed treatment with respect to manufacturing yield, circuit functionality, error tolerance and growth speed is pursued. As a general conclusion, it is shown that errors are pattern dependent, hence the faults occurring in the assembled QCA circuits are physically and logically different.

8Gb/s capacitive low power and high speed 4-PWAM transceiver design

Abstract: In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other works. A novel technique is proposed to reduce power and to increase speed by using capacitive driven low swing transceiver. The proposed design saves 1.74~2.4x power and 4x higher data rate than conventional designs. To implement 4-PWAM transmitter new phase controller and adaptive capacitance network are designed. At receiver side, new architectures for PWM and PAM demodulation are proposed.

Parallel growth and healing of DNA self-assembly for interconnects

Abstract: Self-assembly has been employed in nano-technology to build crystals using individual components (commonly referred to as tiles) with limited control. Templates of regular lattice structures for two-dimensional scaffolds and interconnects have been recently implemented by self-assembly. This study proposes a diagonally based growth scheme that is applicable to these templates of interconnects (as an example). Differently from previous techniques (mostly sequential in execution), growth is allowed along two different directions in the aggregate, thus permitting a parallel mode of operation. This is made possible by utilising a tile set and binding scheme to allow multiple seed tiles to grow along the main diagonal of the pattern. The conditions by which this type of new growth is possible at a reduced error occurrence in mismatched tiles, are presented; error tolerance is achieved by employing healing and so-called robust generation of the seed tiles, thus ensuring that pattern growth is controlled along both directions. Simulation results are presented under different scenarios of growth direction (inclusive of backward growth for healing).

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Abstract: Welcome to the 20th edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2010 held in Providence, Rhode Island. Since its inception in 1991 in Kalamazoo, GLSVLSI has become a premier venue for the dissemination of manuscripts of the highest quality in all areas as related to VLSI. This year GLSVLSI is in the "Ivy League" itself as it is hosted on the beautiful campus of Brown University. We are confident that you will enjoy the surrounding sites as well as the program over the three days of activity. As for the technical meeting, GLSVLSI2010 was a resounding success: 165 papers were submitted, of which 50 papers were accepted for oral presentation at the symposium (a 30% acceptance rate). With poster papers, a total of 87 papers will be presented at the symposium and published in the proceedings. The final technical program consists of 30 full presentations and 20 short presentation in 12 oral sessions and 37 posters in 2 poster sessions. Differently from previous venues, the technical program of GLSVLSI2010 has three parallel sessions to allow longer presentations and discussions; a total of 10 normal sessions covering topics such as VLSI circuits, testing CAD, low power and emerging technologies/post-CMOS have been included. The recipients of the Best Paper Award this year are Marisha Rawlins and Ann Gordon-Ross for the manuscript "Lightweight Runtime Control Flow Analysis for Adaptive Loop Caching"; congratulations on this resounding accomplishment. GLSVLSI 2010 starts off Sunday afternoon, May 16th, with an exciting line up of invited speakers on a broad range of issues related to VLSI design, including NoC-based reconfigurable systems, microprocessor power impacts, and neurosensor arrays for implantable brain communication. The Sunday talks are free for all registered attendees of the conference. On Monday, our keynote speaker is Ron Weiss (MIT) who will be presenting some of his latest research in synthetic biology. Finally, on Tuesday, the technical program includes an invited special session on "System Level Power Management Algorithms and Optimization Methodologies".

Multiple Error Detection in DNA Self-Assembly Using Coded Tiles

Abstract: This brief deals with error detection in deoxyribonucleic acid self-assembly; coding and mapping functions are utilized to assess a correct (error-free) attachment of a tile to a site in the growth process. The proposed approach utilizes the coding/mapping features of the bonds in the tile set by utilizing single and multiple (combined) properties. Properties are combined through an iterative process that considers the aggregate of the intended pattern through coding of the bonds. As a widely used pattern and instantiation of this process, the Sierpinski Triangle self-assembly is analyzed in detail. The properties proposed for the Sierpinski Triangle allow extending single-error detection to the scenario of multiple clustered errors.

Modeling Gross Damage in Tile-Based Nanomanufacturing by DNA Self-Assembly

Abstract: This paper proposes a novel model for gross damage as occurring in tile-based nanomanufacturing by DNA self-assembly. Gross damage occurs due to exogenous agents (such as radiation and tip-sample interactions) and is modeled as a hole (with a large number of empty tile sites) in the aggregate of the self-assembly. A stochastic analysis based on Markov chains for the tile binding process is pursued for regrowth of the tiles. This analysis establishes resilience as the probability to regrow the target pattern in the area affected by the gross damage. The conditions by which regrowth of a hole is favorable (i.e., at high resilience) compared with normal growth are established by considering temperature of aggregation and bond energy. As examples, two patterns for nano interconnects are analyzed based on the proposed model.

An Analytical Error Model for Pattern Clipping in DNA Self-Assembly

Abstract: Large and complex structures commonly referred to as patterns can be generated using DNA-like self-assembly Self-assembly has an algorithmic nature, that is suitable for diverse applications in nano computing and manufacturing This paper deals with the error characterization and modeling encountered when only a partial pattern is grown by DNA self-assembly Partial growth is accomplished by clipping and utilizing specific structures (such as rulers, decoders and staircases) to allow the control of the growth process, ie the self-assembly can be either stopped or redirected as required Initially the characterization of tile errors that are possible when clipping a pattern (such as the Sierpinski Triangle pattern), is presented with particular emphasis on the effects of erroneous aggregation in the capabilities of the clipping structures An analytical approach is proposed to assess the effects of errors on clipping, this approach utilizes a geometric technique by which growth can be assessed with respect to the features of the desired (clipped) pattern Simulation results are also presented, an excellent agreement between simulated and analytical results is achieved