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Francois Lime

Researcher at Rovira i Virgili University

Publications -  69
Citations -  775

Francois Lime is an academic researcher from Rovira i Virgili University. The author has contributed to research in topics: MOSFET & Gate dielectric. The author has an hindex of 15, co-authored 66 publications receiving 705 citations. Previous affiliations of Francois Lime include Grenoble Institute of Technology & Los Angeles Harbor College.

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Proceedings ArticleDOI

75 nm damascene metal gate and high-k integration for advanced CMOS devices

TL;DR: In this article, an advanced CMOS process has been proposed which includes key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT.
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A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects

TL;DR: In this article, a drain-current model for undoped symmetric double-gate MOSFETs is proposed, where channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2D Poisson equation.
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Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

TL;DR: In this paper, the effective mobility has been characterized at various temperatures for NMOS and PMOS devices, and the electron mobility is lower than in SiO 2, whereas the hole mobility is relatively unaffected at room temperature but also degraded at low temperatures.
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Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra-thin gate oxides

TL;DR: In this article, the amplitude of the effective mobility is found to be degraded significantly with oxide scaling, and the mobility attenuation at high field associated to the surface roughness remains unchanged with oxide thickness reduction.
Proceedings ArticleDOI

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

TL;DR: In this article, a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths is presented.