The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors. Field-effect transistors (FETs) with semiconducting channels made from 2D materials are known to have fewer problems with short-channel effects than devices comprising 3D semiconductors. In this Review, a mathematical framework to evaluate the performance of FETs is outlined with a focus on the properties of 2D materials, such as graphene, transition metal dichalcogenides, phosphorene and silicene.

Two-dimensional semiconductors for transistors

Physically unclonable function (PUF) circuits are low-cost cryptographic primitives used for generation of unique, stable and secure keys or chip IDs for device authentication and data security in high-performance microprocessors [1][2][3][7]. The volatile nature of PUFs provides a high level of security and tamper resistance against invasive probing attacks compared to conventional fuse-based key storage technologies [4]. A process-voltage-temperature (PVT) variation-tolerant all-digital PUF array targeted for on-die generation of 100% stable, device-specific, high-entropy keys is fabricated in 22nm tri-gate high-κ metal-gate CMOS technology [5], featuring: i) a hybrid delay/cross-coupled PUF circuit where interaction of 16 minimum-sized, variation-impacted transistors determines resolution dynamics, ii) a temporal majority voting (TMV) circuit to stabilize occasionally unstable bits, resulting in 53% reduction in instability, iii) burn-in hardening to reinforce manufacturing-time PUF bias, resulting in 22% reduction in bit-errors, iv) soft dark bits for run-time identification and sequestration of highly unstable bits during field operation, resulting in 78% lower bit-errors, v) 19× separation between inter- and intra-PUF Hamming distance, enabling die-specific keys, vi) autocorrelation factor≈0 and entropy=0.9997, while passing NIST randomness tests, vii) high tolerance to voltage and temperature variation with 82% reduction in average Hamming-distance using a 100-cycle dark bit window, viii) in-situ PUF hardening by leveraging directed NBTI aging to improve stability during field operation, and ix) ultra-low energy consumption of 0.19pJ/b with compact bitcell layout of 4.66μm2 (Fig. 16.2.7a).

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

Abstract: In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

/pdf/implementation-of-2-bit-multiplier-circuit-using-pass-2amlacsv.pdf

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator at 1.8v single ended supply voltage and simulations are carried out to indicate the functionality of the proposed full adder circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

/pdf/implementation-of-1-bit-full-adder-circuit-using-pass-1h1m6bq3.pdf

G. Gupta

Papers

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic

Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic