C
C. Staus
Researcher at Intel
Publications - 2
Citations - 310
C. Staus is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Subthreshold slope. The author has an hindex of 2, co-authored 2 publications receiving 293 citations.
Papers
More filters
Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings Article
A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB
Ruth A. Brain,Andre Baran,Nabhendra Bisnik,H.-P. Chen,S.-J. Choi,A. Chugh,M. Fradkin,Timothy E. Glassman,F. Hamzaoglu,E. Hoggan,R. Jahan,M. Jamil,C.-H. Jan,J. Jopling,H. Kan,Rahim Kasim,S. Kirby,S. Lahiri,B.-C Lee,Daniel R. Lenski,J. Limb,Nick Lindert,M. Musorrafiti,J. Neulinger,L. Rockford,Joodong Park,Kanwal Jit Singh,C. Staus,Joseph M. Steigerwald,B. Turkot,P. Vandervoorn,R. Venkatesan,Stephen Y. Wu,J.-Y. Yeh,Yih Wang,Z. Zhang,Kevin Zhang +36 more
TL;DR: In this article, a 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices.