R
Ruth A. Brain
Researcher at Intel
Publications - 32
Citations - 1130
Ruth A. Brain is an academic researcher from Intel. The author has contributed to research in topics: Layer (electronics) & Transistor. The author has an hindex of 13, co-authored 32 publications receiving 1092 citations.
Papers
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Proceedings ArticleDOI
A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array
Sanjay Natarajan,Mark Armstrong,M. Bost,Ruth A. Brain,Mark R. Brazier,C.-H. Chang,V. Chikarmane,Michael A. Childs,H. Deshpande,K. Dev,G. Ding,Tahir Ghani,Oleg Golonzka,W. Han,Jun He,R. Heussner,Robert James,I. Jin,C. Kenyon,S. Klopcic,Seung Hwan Lee,Mark Y. Liu,S. Lodha,B. McFadden,Anand Portland Murthy,L. Neiberg,J. Neirynck,Paul A. Packan,S. Pae,C. Parker,C. Pelto,L. Pipes,J. Sebastian,J. Seiple,Sell Bernhard,Swaminathan Sivakumar,B. Song,K. Tone,T. Troeger,Cory E. Weber,M. Yang,Yeoh Andrew W,Kevin Zhang +42 more
TL;DR: In this paper, a 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques.
Patent
Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
TL;DR: In this paper, multiple level interconnect structures and methods for fabricating the interconnect structure are disclosed, and metal layers are used to provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer.
Patent
Use of conductive electrolessly deposided etch stop layers, liner layers and via plugs in interconnect structures
TL;DR: In this article, multiple level interconnect structures and methods for fabricating the interconnect structure are disclosed, and the metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer.