Goutham Arutchelvan

TL;DR: The obstacles and paths to a scaled 2D CMOS solution are highlighted and the baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows to identify the most promising 2D material and device design.

TL;DR: A semi-classical model is developed to identify the main mechanisms and trajectories for carrier injection at MoS2 contacts and it is found that the transmission line model could significantly overestimate the transfer length and hence the contact resistivity for monolayer and bilayer MoS 2.

TL;DR: In this article, the authors show that scaling the top-contact length to 13nm induces no penalty on the electrical characteristics for CVD MoS 2 FETs and demonstrate this for devices with different gate-oxides and operating in both channel and contact-limited regimes, thus confirming carrier injection at the edge of the contact metal.

TL;DR: Side contacted source/drain, vertically-stacked 2D sheets and fork-sheet architecture are highlighted as key enablers of 2D-FET technology for multiple advanced nodes, using experimentally realistic mobility and Schottky barrier height conditions.