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Abhinav Gaur
Researcher at Katholieke Universiteit Leuven
Publications - 18
Citations - 249
Abhinav Gaur is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Diode & Admittance. The author has an hindex of 8, co-authored 18 publications receiving 148 citations. Previous affiliations of Abhinav Gaur include Rochester Institute of Technology.
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Proceedings ArticleDOI
2D materials: roadmap to CMOS integration
Cedric Huyghebaert,Tom Schram,Quentin Smets,T. Kumar Agarwal,Devin Verreck,Steven Brems,Alain Phommahaxay,D. Chiappe,S. El Kazzi,C. Lockhart de la Rosa,Goutham Arutchelvan,Daire J. Cott,Jonathan Ludwig,Abhinav Gaur,Surajit Sutar,Alessandra Leonhardt,Daniil Marinov,D. Lin,Matty Caymax,Inge Asselberghs,Geoffrey Pourtois,Iuliana Radu +21 more
TL;DR: The obstacles and paths to a scaled 2D CMOS solution are highlighted and the baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows to identify the most promising 2D material and device design.
Proceedings ArticleDOI
Ultra-scaled MOCVD MoS 2 MOSFETs with 42nm contact pitch and 250µA/µm drain current
Quentin Smets,Benjamin Groven,Matty Caymax,Iuliana Radu,Goutham Arutchelvan,J. Jussot,Devin Verreck,Inge Asselberghs,Ankit Nalin Mehta,Abhinav Gaur,Dennis Lin,Salim El Kazzi +11 more
TL;DR: In this article, the authors show that scaling the top-contact length to 13nm induces no penalty on the electrical characteristics for CVD MoS 2 FETs and demonstrate this for devices with different gate-oxides and operating in both channel and contact-limited regimes, thus confirming carrier injection at the edge of the contact metal.
Journal ArticleDOI
MoS2 Functionalization with a Sub-nm Thin SiO2 Layer for Atomic Layer Deposition of High-κ Dielectrics
Haodong Zhang,Goutham Arutchelvan,Johan Meersschaut,Abhinav Gaur,Thierry Conard,Hugo Bender,Dennis Lin,Inge Asselberghs,Marc Heyns,Iuliana Radu,Wilfried Vandervorst,Annelies Delabie +11 more
TL;DR: In this paper, the surface of a polycrystalline 2D MoS2 film is functionalized with SiO2 to enable the atomic layer deposition (ALD) of thin and continuous Al2O3 and HfO2 layers.
Proceedings ArticleDOI
Wafer-scale integration of double gated WS 2 -transistors in 300mm Si CMOS fab
Inge Asselberghs,Quentin Smets,Tom Schram,Benjamin Groven,Devin Verreck,Aryan Afzalian,Goutham Arutchelvan,Abhinav Gaur,Daire J. Cott,Thibaut Maurice,Steven Brems,Koen Kennes,Alain Phommahaxay,E. Dupuy,D. Radisic,J-F de Marneffe,A. Thiam,W. Li,Katia Devriendt,Cedric Huyghebaert,D. Lin,Matty Caymax,P. Morin,Iuliana Radu +23 more
TL;DR: In this article, double-gated WS 2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab and an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance.
Journal ArticleDOI
Impact of device scaling on the electrical properties of MoS2 field-effect transistors.
Goutham Arutchelvan,Quentin Smets,Devin Verreck,Zubair Ahmed,Abhinav Gaur,Surajit Sutar,J. Jussot,Benjamin Groven,Marc Heyns,Dennis Lin,Inge Asselberghs,Iuliana Radu +11 more
TL;DR: In this paper, the scaling behavior of large-area grown MoS2 material with channel length down to 30nm and capacitive effective oxide thickness (CET) down to 1.9nm was investigated.