Heng-Yuan Lee

TL;DR: In this paper, a resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided, where each of the sets includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance changing layer and the barrier layer.

TL;DR: This work proposes a thermal-aware bitline (BL) voltage bias (VBL-R) scheme (TABB) for current-mode read with 1.6x faster read speed to overcome temperature-dependent fluctuation in the base-emitter voltage difference (VBE) of BJT.

TL;DR: In this article, a memory cell of a resistive random access memory and a manufacturing method of the memory cell is described, which includes the following steps: a first electrode is formed. A metal oxide layer is formed on the first electrode.

TL;DR: In this paper, a method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at first a first plug is formed so that the first plug was connected to the drain of the transistor, depositing an etching stop layer on the firstplug and the inter layer dielectrics layer; depositing a first insulating layer, on the etch stop layer, forming a second plug on the second plug, and forming at least an opening in the mold

TL;DR: In this paper, a method of manufacturing dynamic random access memory (DRAM) cylindrical capacitors is presented, where a dielectric layer having an opening is disposed on the substrate, wherein the opening exposes the polysilicon plug.