Showing papers by "Jan Craninckx published in 2010"

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS

Abstract: Wireless environments, high data rates and increased digitization require A/D converters with high dynamic range and large bandwidth at the lowest possible power consumption. A fully flexible continuous-time (CT) Δ Σ with programmable bandwidth, resolution and power consumption in 1.2 V 90 nm CMOS is presented able to satisfy those demands. By introducing flexibility into the core building blocks, a DR of 67/72/78/83 dB is achieved in maximum performance mode for WLAN, DVB, UMTS and BT for a power consumption of 6.8/5.5/6.4/5.0 mW, respectively. GSM operation is also feasible with a DR of 87 dB. For a given bandwidth, the flexibility allows to obtain the lowest power consumption for a desired performance. The overall energy efficiency is reached with a single-bit CT Δ Σ modulator avoiding high speed DEM circuits. Its low power consumption especially for high bandwidths is realized thanks to architecture and circuit level optimization. Linearity enhanced integrators, a threshold configurable comparator enabling loop delay compensation and optimized DAC implementations for jitter and avoiding signal dependency in the feedback pulses due to a large voltage swing are employed to increase the performance. The respective FOM equals 0.24/0.27/0.41/0.85 pJ per conversion.

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS

Abstract: Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the required calibration effort.

A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

Abstract: A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm2 synthesizer, which is appropriate for use in a Software-Defined Radio, features noise cancellation and digital phase modulation and consumes less than 30 mW.

A 5 mm $^{2}$ 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

Abstract: A 5 mm2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.

A 5mm 2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver

Abstract: The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio (SDR) in deeply scaled CMOS. This is enhanced with the advent of LTE, a standard that is inherently so flexible that an SDR is its most economical implementation. This work presents an answer to that need with the development of a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS

Abstract: A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2.

A 0.5 mm $^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler

Abstract: A highly flexible receiver chain based on RF-sampling and discrete-time signal processing in the charge domain for SDR applications is presented. A compact switched-inductor variable-gain front-end provides multiband low noise amplification and RF-selectivity with reduced area penalties. Strong selectivity at RF was obtained through a novel discrete-time decimating bandpass filter with triangular weighted filter taps. Decimation filters with programmable number of taps offer flexible rate decimation. A power scalable discrete-time baseband filter was implemented in-order to minimize static power consumption. The 90-nm digital CMOS implementation achieves a noise figure of 5.1 dB, a variable gain range of more than 60 dB with +1 dBm IIP3 and +50 dBm IIP2. This is achieved for power figures competitive with dedicated solutions. The receiver, frequency synthesizer excluded, occupies only 0.5 mm2 .

A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS

Abstract: A 0.4mm2 low-power fully-reconfigurable continuous-time (CT) feedforward ΔΣ ADC for 4G radios is implemented in 90nm CMOS. By reconfiguring the topology architecture, quantizer bits, biasing current and component parameters, optimal power consumption can be achieved for every mode. The modulator achieves a DR of 85/78/76/72/58dB for GSM/BT/UMTS/DVB-H/WLAN with 2.8/2.6/3.6/4.9/8.5mW from 1V supply. The FOM is 0.68/0.5/0.28/0.27/0.41pJ/conv.

A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS

Abstract: A 2.4 GHz 4th order BP ΔΣ ADC is presented. The feedforward topology uses Gm-LC resonators that can be calibrated in frequency. The quantizer is split in 6 interleaved comparators to relax speed. Clocked at 6.1 GHz, it achieves a DR of 43 dB in 80 MHz consuming 52.8 mW. Implemented in 40 nm CMOS, it achieves a FoM of 3.6 pJ/conv. step, which is to date the lowest published value for RF BP ADCs.

A 0.045mm 2 0.1–6GHz reconfigurable multi-band, multi-gain LNA for SDR

Abstract: A low area fully reconfigurable multi-band LNA array based on active feedback amplifiers with mixed resistive and switched inductor loads is presented. The 90nm baseline digital CMOS implementation covers the entire frequency range of interest for SDR from 0.1 to 6GHz with a dynamic gain range from 0dB to 22dB. A noise figure as low as 2.7dB and an input-referred linearity IIP3 of −4dBm at 16dB gain is achieved. An IIP3 of +9dBm is reached in low gain mode to allow for high signal and interferer power at the antenna input. The LNA draws between 10 and 26mA from a 1.2V supply. The active area of the array is only 0.045mm2.

A sub-3dB NF voltage-sampling front-end with +18dBm IIP 3 and +2dBm blocker compression point

Abstract: A highly-linear 400MHz-3GHz RF front-end is presented. At full gain of 16dB, the 2V LNA and passive mixer boosts 1dB out-of-band blocker compression up to +2dBm, and obtains an untuned, uncalibrated out-of-band IIP 3 of +18dBm and IIP 2 of +61dBm. A NF of less than 3dB is achieved for just 6.5mA front-end current consumption (excluding LO generation) at an area of 0.08mm2 in 90nm digital CMOS. This front-end therefore paves the way to relaxing the antenna filter requirements.

A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS

Abstract: Digital-intensive PLL architectures emerge [1]–[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz–12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1–2MHz. At 7GHz, the 0.28mm2 PLL achieves −144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW.

Versatile Spectrum Sensing on Mobile Devices

Abstract: Spectrum sensing is a key aspect in the realization of opportunistic radios, which will allow a significantly more efficient usage of the scarce spectrum resources. This paper presents a solution to upgrade mobile devices with spectrum sensing capabilities. A versatile digital component is proposed to meet a wide variety of use cases, at low cost and low power overhead. Complementary reconfigurable analog front-ends make the radio ready for upgrading wireless connectivity thanks to availability of information on spectrum occupancy.

An area efficient digital amplitude modulator in 90nm CMOS

Abstract: This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of −2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving −26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm2 chip area.

A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS

Abstract: A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.

A compact digital amplitude modulator in 90nm CMOS

Abstract: This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2 chip area.

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation

Abstract: A wide tuning range LO generation architecture for software defined radio is presented. A dual VCO approach followed by a programmable divider chain based on high-speed dynamic CMOS latches provides full rail-to-rail operation with low power consumption. The 1.2V 90nm CMOS implementation achieves a VCO tuning range between 6 to 13.6GHz for a power consumption between 3.5 to 13.4mW and phase noise figure of merit of 182dBc/Hz measured at 3MHz offset from a 12GHz carrier. The VCO-multiplexer and divider chain consumes between 5.9 to 8.1mW for this frequency range.