Mass spectrometry (MS) is a sensitive, specific and versatile analytical technique in the clinical laboratory that has recently undergone rapid development. From initial use in metabolic profiling, it has matured into applications including clinical toxicology assays, target hormone and metabolite quantitation, and more recently, rapid microbial identification and antimicrobial resistance detection by matrix assisted laser desorption ionization-time of flight mass spectrometry (MALDI-TOF MS). In this mini-review, we first succinctly outline the basics of clinical mass spectrometry. Examples of hard ionization (electron ionization) and soft ionization (electrospray ionization, MALDI) are presented to demonstrate their clinical applications. Next, a conceptual discourse on mass selection and determination is presented: quadrupole mass filter, time-of-flight mass spectrometer and the Orbitrap; and MS/MS (tandem-in-space, tandem-in-time and data acquisition), illustrated with clinical examples. Current applications in (1) bacterial and fungal identification, antimicrobial susceptibility testing and phylogenetic classification, (2) general unknown urine toxicology screening and expanded new-born metabolic screening and (3) clinical metabolic profiling by gas chromatography are outlined. Finally, major limitations of MS-based techniques, including the technical challenges of matrix effect and isobaric interference; and novel challenges in the post-genomic era, such as protein molecular variants, are critically discussed from the perspective of service laboratories. Computer technology and structural biology have played important roles in the maturation of this field. MS-based techniques have the potential to replace current analytical techniques, and existing expertise and instrument will undergo rapid evolution. Significant automation and adaptation to regulatory requirements are underway. Mass spectrometry is unleashing its potentials in clinical laboratories.

https://hub.hku.hk/bitstream/10722/262366/1/content.pdf

Clinical Mass Spectrometry in the Bioinformatics Era: A Hitchhiker's Guide.

This paper proposes a time-residue feedback scheme to balance resolution and complexity in a cell-based time-to-digital converter (TDC). The time residue is amplified and fed back into a cyclic-ring Vernier recursively until it cannot be detected correctly. Only one variable-resolution cyclic-ring Vernier and one tunable delay-chain time amplifier (TA) are adopted. Both coarse and fine oscillators of the proposed Vernier which are designed by the same variable-resolution digital controlled oscillator can be switched off to decrease ground bounce during TA activities. With various control codes, the TDC resolution is also programmable. The test application-specified integrated circuit which has a 13-b resolution and occupies 0.02 mm2 in TSMC 65-nm CMOS process can operate in either feedback or feedforward mode. In feedback mode, the measurements of sampling rate, resolution, input range, differential nonlinearity, and integral nonlinearity are 10 MHz, 0.98 ps, 5.76 ns, ± 0.8 LSB, and ± 2.2 LSB, respectively; it also consumes 3 mW at 1 V supply voltage. The sampling rate, resolution, and power dissipation of the feedforward operation are 250 MHz, 6.01 ps, and 17.5 mW, respectively.

Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback

Memory systems are crucial to the performance, power, and cost of high-performance computing systems. Recently, multiple factors are driving the need for more complex, deep memory hierarchies. However, architects and customers are struggling to design memory systems that effectively balance multiple, often competing, factors in this large, multidimensional, and fast-moving design space. In this paper, we systematically explore the organization of heterogeneous memory systems on a framework called Siena. Siena facilitates quick exploration of memory architectures with flexible configurations of memory systems and realistic memory workloads. We perform a design space exploration on 22 proposed memory systems using eight relevant workloads. Our results show that horizontal organizations of memories can achieve higher performance than vertical organizations when the distribution of memory traffic balances the performance gap between memories. However, the coupling effects through shared resources and application behaviors could negate the advantage of high-performance memory in horizontal organizations.

Siena: exploring the design space of heterogeneous memory systems

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 $\times $ 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.

30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links

Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although 8Gb GDDR5X can operate at 12Gb/s [3] by increasing the burst length (BL) from 8 to 16, a degradation in system performance at a data granularity of 64B is seen. The I/O specification, using PLL clocking that additionally causes PLL jitter, has not changed much compared with GDDR5. To overcome these issues, GDDR6 introduced a dual channel for a data granularity of 32B with a BL16, per-bit training of l/ REF , and an equalizer with PLL-less clocking. This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process.

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process. Furthermore, this paper optimizes clock- and power-domain crossings and adopts split-die architecture to improve signal integrity (SI). This GDDR6 operates 16 Gb/s/pin with 1.15 V and achieves 18 Gb/s/pin with 1.35 V in the DRAM process.

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second conversion as a combination of the Vernier delay line (VDL) and TA in order to implement high resolution. Through the combination of VDL and TA, the area is reduced compared with the single VDL. The proposed TDC has been implemented and simulated in a 65-nm CMOS process with an active core size of um 0.22 mm2. The input range is over 1p, and the minimum time resolution is 2ps with a core power consumption of 69.7 mW.

A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

Ji-Hak Yu

Papers

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

An inverter layout technique for propagation delay minimization