Proceedings ArticleDOI
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Yoon-Joo Eom,Young-Sik Kim,Min-Su Ahn,Yong-Hun Kim,Sang-Hoon Jung,Sung-Geun Do,Chang-Yong Lee,Jae-Sung Kim,Dong-seok Kang,Kyung-Bae Park,Jung-Bum Shin,Jong-Ho Lee,Seung-Hoon Oh,Sang-Yong Lee,Ji-Hak Yu,Ji-Suk Kwon,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Min-Woo Won,Gun-hee Cho,Hyun-Soo Park,Hyung-Kyu Kim,Jeong-Woo Lee,Seung-Hyun Cho,Keon-woo Park,Jae-Koo Park,Lee Yong-Jae,Yong-Jun Kim,Young-Hun Seo,Beob-Rae Cho,Chang-Ho Shin,Chan-Yong Lee,Youngseok Lee,Yoon-Gue Song,Sam-Young Bang,Youn-sik Park,Seouk-Kyu Choi,Byeong-Cheol Kim,Gong-Heum Han,Seung-Jun Bae,Hyuk-Jun Kwon,Jung-Hwan Choi,Young-Soo Sohn,Kwang-Il Park,Seong-Jin Jang +48 more
- pp 204-206
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TLDR
This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.Abstract:
Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although 8Gb GDDR5X can operate at 12Gb/s [3] by increasing the burst length (BL) from 8 to 16, a degradation in system performance at a data granularity of 64B is seen. The I/O specification, using PLL clocking that additionally causes PLL jitter, has not changed much compared with GDDR5. To overcome these issues, GDDR6 introduced a dual channel for a data granularity of 32B with a BL16, per-bit training of l/ REF , and an equalizer with PLL-less clocking. This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process.read more
Citations
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Proceedings ArticleDOI
Siena: exploring the design space of heterogeneous memory systems
Ivy Bo Peng,Jeffrey S. Vetter +1 more
TL;DR: This paper systematically explore the organization of heterogeneous memory systems on a framework called Siena, which facilitates quick exploration of memory architectures with flexible configurations of memory systems and realistic memory workloads.
Proceedings ArticleDOI
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM
Yong-Hun Kim,Hyung-Jin Kim,Jaemin Choi,Min-Su Ahn,Dongkeon Lee,Seung-Hyun Cho,Dong-Yeon Park,Young-Jae Park,Min-Soo Jang,Yong-Jun Kim,Jinyong Choi,Sung-Woo Yoon,Jae-Woo Jung,Jae-Koo Park,Jae-Woo Lee,Dae-Hyun Kwon,Hyung-Seok Cha,Si-Hyeong Cho,Seong-hoon Kim,Jihwa You,Kyoung-Ho Kim,Dae Hyun Kim,Byung-Cheol Kim,Young-Kwan Kim,Jun-Ho Kim,Seouk-Kyu Choi,Chan-Young Kim,Byongwook Na,Hye-In Choi,Reum Oh,Jeong-Don Ihm,Seung-Jun Bae,Nam Sung Kim,Jung-Bae Lee +33 more
TL;DR: In this article, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size, and the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier with dedicated Vthis articles for a 1-tap DFE.
Proceedings ArticleDOI
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Kyung-Soo Ha,Chang-Kyo Lee,Dongkeon Lee,Daesik Moon,Jin-Hun Jang,Hyong-Ryol Hwang,Hyung-Joon Chi,Junghwan Park,Seung-Jun Shin,Duk-ha Park,Kim Sang-Yun,Lim Suk-Hyun,Ki-Won Park,Choi Yeon-Kyu,Young-Hwa Kim,Young Hoon Son,Hyunyoon Cho,Byongwook Na,Hyo-Joo Ahn,Seungseob Lee,Seouk-Kyu Choi,Youn-sik Park,Seok-Hun Hyun,Soo-bong Chang,Hyuck-Joon Kwon,Jung-Hwan Choi,Tae-Young Oh,Young-Soo Sohn,Kwang-II Park,Seong-Jin Jang +29 more
TL;DR: This paper presents a 1st generation 10nm-class process LPDDR5, which includes novel schemes that increase the maximum bandwidth, such as WCK clocking and non-target ODT (NT-ODT) and power consumption is reduced by low power schemes.
Journal ArticleDOI
Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane
Timothy M. Hollis,Eric J. Stave,Dave Ovard,Roy Greeff,Worfgang Spirkl,Martin Brox,Jennifer E. Taylor,Justin D. Butterfield +7 more
TL;DR: As semiconductor technologies have matured and computing applications have proliferated, memory technology has experienced a corresponding evolution and diversification to address application-specific requirements and topological targets.
Journal ArticleDOI
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Min-Su Ahn,Yong-Hun Kim,Lee Yong-Jae,Dong-seok Kang,Sung-Geun Do,Chang-Yong Lee,Gun-hee Cho,Jae-Koo Park,Jae-Sung Kim,Kyung-Bae Park,Seung-Hoon Oh,Sang-Yong Lee,Ji-Hak Yu,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Hyun-Soo Park,Jeong-Woo Lee,Seung-Hyun Cho,Keon-woo Park,Yong-Jun Kim,Young-Hun Seo,Chang-Ho Shin,Chan-Yong Lee,Sam-Young Bang,Youn-sik Park,Seouk-Kyu Choi,Byung-Cheol Kim,Gong-Heum Han,Seung-Jun Bae,Hyuk-Jun Kwon,Jung-Hwan Choi,Young-Soo Sohn,Kwang-Il Park,Seong-Jin Jang,Gyo-Young Jin +38 more
TL;DR: This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process.
References
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Proceedings ArticleDOI
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Seung-Jun Bae,Young-Soo Sohn,Kwang-ll Park,Kyoung-Ho Kim,Dae-Hyun Chung,Jingook Kim,Si-Hong Kim,Min-Sang Park,Jae-Hyung Lee,Sam-Young Bang,Ho-Kyung Lee,In-Soo Park,Jae-Sung Kim,Dae Hyun Kim,Hye-Ran Kim,Yong-Jae Shin,Cheol-Goo Park,Gil-Shin Moon,Ki-Woong Yeom,Kang-Young Kim,Jae-Young Lee,Hyang-ja Yang,Seong-Jin Jang,Joo Sun Choi,Young-Hyun Jun,Kinam Kim +25 more
TL;DR: This work tackles challenges in GDDR5 such as clock jitter and signal integrity with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding.
Proceedings ArticleDOI
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
Chang-Kyo Lee,Yoon-Joo Eom,Jin-Hee Park,Junha Lee,Hye-Ran Kim,Ki-Han Kim,Young Sang Choi,Ho-Jun Chang,Jong-Hyuk Kim,Jong-Min Bang,Seung-Jun Shin,Hanna Park,Su-Jin Park,Young-Ryeol Choi,Hoon Lee,Kyong-Ho Jeon,Jae-Young Lee,Hyo-Joo Ahn,Kyoung-Ho Kim,Jung-Sik Kim,Soo-bong Chang,Hyong-Ryol Hwang,Du-Yeul Kim,Yoon-Hwan Yoon,Seok-Hun Hyun,Joon-Young Park,Yoon-Gyu Song,Youn-sik Park,Hyuck-Joon Kwon,Seung-Jun Bae,Tae-Young Oh,In-Dal Song,Yong-Cheol Bae,Jung-Hwan Choi,Kwang-Il Park,Seong-Jin Jang,Gyo-Young Jin +36 more
TL;DR: A 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.
Proceedings ArticleDOI
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution
Hye-Yoon Joo,Seung-Jun Bae,Young-Soo Sohn,Young-Sik Kim,Kyung-Soo Ha,Min-Su Ahn,Young-Ju Kim,Yong-Jun Kim,Ju-Hwan Kim,Won-Jun Choi,Chang-Ho Shin,Kim Soo Hwan,Byeong-Cheol Kim,Seung-Bum Ko,Kwang-Il Park,Seong-Jin Jang,Gyo-Young Jin +16 more
TL;DR: To cover operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs, this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty-cycle correction modes, CML-to-CMOS converters with wide range operation, active resonant loads at the end of WCK lane, and an on-chip de-emphasis circuit at a 4- to-1 multiplexer output.
Proceedings ArticleDOI
23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications
Martin Brox,Mani Balakrishnan,Martin Broschwitz,Cristian Chetreanu,Stefan Dietrich,Fabien Funfrock,Marcos Alvarez Gonzalez,Thomas Hein,Eugen Huber,Daniel Lauber,Milena Ivanov,Maksim Kuzmenka,Chris Mohr,Francisco Emiliano Munoz,Juan Ocon Garrido,Swetha Padaraju,Sven Piatkowski,Jan Pottgiesser,Peter Pfefferl,Manfred Plan,Jens Polney,Stefan Rau,Michael Richter,Ronny Schneider,Ralf Oliver Seitter,Wolfgang Spirkl,Marc Walter,Jorg Weller,Filippo Vitale +28 more
TL;DR: An 8Gb GDDR5X DRAM has been developed reaching a data rate of 12Gb/s/pin, which surpasses the fastest published GDDR5 by 33%.
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