Yoon-Joo Eom

TL;DR: A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented.

TL;DR: A 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.

TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.

TL;DR: In this paper, a multi-channel semiconductor device is described, where a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on a substrate having a second channel different from the first channel and including the same storage capacity and physical size as the first die.

TL;DR: In this paper, a memory controller and a semiconductor memory device are configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on the reference voltage when the memory device is electrically connected to the controller.