C
Chang-Yong Lee
Researcher at Samsung
Publications - 7
Citations - 89
Chang-Yong Lee is an academic researcher from Samsung. The author has contributed to research in topics: Dram & Synchronization. The author has an hindex of 4, co-authored 7 publications receiving 72 citations.
Papers
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Journal ArticleDOI
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
Tae-Young Oh,Hoe-ju Chung,Jun-Young Park,Ki-Won Lee,Seung-Hoon Oh,Su-Yeon Doo,Hyoung-Joo Kim,Chang-Yong Lee,Hye-Ran Kim,Jong-ho Lee,Jin-Il Lee,Kyung-Soo Ha,Young-Ryeol Choi,Young-Chul Cho,Yong-Cheol Bae,Tae-Seong Jang,Chul-Sung Park,Kwang-Il Park,Seong-Jin Jang,Joo Sun Choi +19 more
TL;DR: A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented and the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for D QS tree delay tracking.
Proceedings ArticleDOI
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Yoon-Joo Eom,Young-Sik Kim,Min-Su Ahn,Yong-Hun Kim,Sang-Hoon Jung,Sung-Geun Do,Chang-Yong Lee,Jae-Sung Kim,Dong-seok Kang,Kyung-Bae Park,Jung-Bum Shin,Jong-Ho Lee,Seung-Hoon Oh,Sang-Yong Lee,Ji-Hak Yu,Ji-Suk Kwon,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Min-Woo Won,Gun-hee Cho,Hyun-Soo Park,Hyung-Kyu Kim,Jeong-Woo Lee,Seung-Hyun Cho,Keon-woo Park,Jae-Koo Park,Lee Yong-Jae,Yong-Jun Kim,Young-Hun Seo,Beob-Rae Cho,Chang-Ho Shin,Chan-Yong Lee,Youngseok Lee,Yoon-Gue Song,Sam-Young Bang,Youn-sik Park,Seouk-Kyu Choi,Byeong-Cheol Kim,Gong-Heum Han,Seung-Jun Bae,Hyuk-Jun Kwon,Jung-Hwan Choi,Young-Soo Sohn,Kwang-Il Park,Seong-Jin Jang +48 more
TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.
Journal ArticleDOI
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Min-Su Ahn,Yong-Hun Kim,Lee Yong-Jae,Dong-seok Kang,Sung-Geun Do,Chang-Yong Lee,Gun-hee Cho,Jae-Koo Park,Jae-Sung Kim,Kyung-Bae Park,Seung-Hoon Oh,Sang-Yong Lee,Ji-Hak Yu,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Hyun-Soo Park,Jeong-Woo Lee,Seung-Hyun Cho,Keon-woo Park,Yong-Jun Kim,Young-Hun Seo,Chang-Ho Shin,Chan-Yong Lee,Sam-Young Bang,Youn-sik Park,Seouk-Kyu Choi,Byung-Cheol Kim,Gong-Heum Han,Seung-Jun Bae,Hyuk-Jun Kwon,Jung-Hwan Choi,Young-Soo Sohn,Kwang-Il Park,Seong-Jin Jang,Gyo-Young Jin +38 more
TL;DR: This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process.
Journal ArticleDOI
모델기반 개발기법과 X-plane을 이용한 무인항공기 비행제어 프로그램 모의비행 검증
TL;DR: The design of operation flight program (OFP) is shown using model-based design(MBD) method which is used in various engineering fields to reduce time and flight risks for development.
Patent
Semiconductor memory device, memory system, and method using bus-invert encoding
TL;DR: In this article, a data inversion circuit is configured to determine whether to invert the second unit data based on the Hamming distance between the first unit data and the second units data.