Youn-sik Park

TL;DR: In this paper, a semiconductor integrated circuit device is connected to an external reference resistor, including an impedance control circuit for generating impedance control codes variable with impedances established by the external resistor.

TL;DR: In this paper, the column redundancy fuse box is connected in common to the plurality of redundant column selection line drivers, and a redundancy enable signal generating portion is connected to the repair address determining portion.

TL;DR: A 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.

TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.

TL;DR: In this article, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM, allowing relatively wide power conductors to be routed on a third metal layer, and thus can provide a more stable power supply to the memory array, and also free some space on first or second metal for routing of additional and/or more widely spaced signal conductors.