Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

Superjunction Power Devices, History, Development, and Future Prospects

The present disclosure describes a methodology for wireless power transmission based on pocket-forming. This methodology may include one transmitter and at least one or more receivers, being the transmitter the source of energy and the receiver the device that is desired to charge or power. The transmitter may identify and locate the device to which the receiver is connected and thereafter aim pockets of energy to the device in order to power it. Pockets of energy may be generated through constructive and destructive interferences, which may create null-spaces and spots of pockets of energy ranged into one or more radii from transmitter. Such feature may enable wireless power transmission through a selective range, which may limit operation area of electronic devices and/or may avoid formation of pockets of energy near and/or over certain areas, objects and people.

Wireless power transmission with selective range

Configurations and methods of wireless power transmission for charging or powering one or more electronic devices inside a vehicle are disclosed. A transmitter capable of single or multiple pocket-forming may be connected to a car lighter, where this transmitter may include a circuitry module and an antenna array integrated within the transmitter, or operatively connected through a cable. This cable may allow the positioning of the antenna array in different locations inside the vehicle suitable for directing RF waves or pockets of energy towards one or more electronic devices. Transmitter's configuration can be accessed by one or more electronic devices through Bluetooth communication in order to set up charging or powering priorities.

Wireless charging and powering of electronic devices in a vehicle

The present disclosure may provide a wireless power system which may be used to provide wireless power transmission (WPT) while using suitable WPT techniques such as pocket-forming. Wireless power system may be used in a wireless powered house for providing power and charge to a plurality of mobile and non-mobile devices. Wireless powered house may include a single base station which may be connected to several transmitters. Base station may manage operation of every transmitter in an independently manner or may operate them as a single transmitter. Connection between base station and transmitters may be achieved through a plurality of techniques including wired connections and wireless connections.

Wireless powered house

Embodiments directed to providing health safety in a wireless power transmission systems are disclosed herein. One embodiment includes a processing apparatus with a processor; a data storage; and one or more wireless power transmitters each including at least two antennas. The one or more wireless power transmitters receive instructions from the processing apparatus that cause the transmitters to transmit RF waves that constructively interfere to provide wirelessly delivered power to one or more receivers. The processing apparatus receives and processes wireless power proscribing data for each respective receiver, respective wireless power proscribing data including at least one user-specified circumstance that a user inputs as to when a respective electronic device coupled with the respective receiver is in use; and the processing apparatus causes transmission of the RF waves by the transmitters in accordance with determining that the at least one user-specified circumstance is not present at the respective electronic device.

System and method for providing health safety in a wireless power transmission system

A novel 500 V reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation. The RC is realized by the internal diode, which consists of two p-i-n diodes (D1 and D2). The two diodes are connected in series. In the RC-state, the current flows through D1 first and then through D2. D2 is embedded in the anode region of the proposed DED-LIGBT and is fully isolated by the deep-oxide trench. In the forward conducting state, D2 is reverse biased and the electrons from the N+ cathode can only flow into the P+ anode. The DEDs reroute the electron current path, and thus, the snapback is avoided. Moreover, by adjusting the width of D2 ( ${W}_{b})$ , the internal diode of the DED structure achieves superior reverse recovery time ( ${t}_{\text {rr}})$ and reverse recovery peak current ( ${I}_{\text {rrm}})$ to the conventional SOI p-i-n diode.

Novel Snapback-Free Reverse-Conducting SOI-LIGBT With Dual Embedded Diodes

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Isolation structure of high-voltage driving circuit

An integrated bootstrap diode emulator, including the high voltage field-effect-transistor (HV-FET), the gate control circuit and the back-gate control circuit, is experimentally proposed base on p-sub/p-epi bipolar-CMOS-DMOS technology for the first time. By adopting the gate and the back-gate control circuits, the charging time of the bootstrap capacitor can be improved by about 27% without any latch-up issues. The measured blocking voltage of the proposed HV-FET is higher than 750 V, which can be embedded in the isolation structure without sacrificing the chip area and is suitable for 600-V motor control system application. Finally, a 600-V-class high voltage gate drive IC with the proposed integrated bootstrap diode emulator is fabricated. The chip size is about 2.1 mm2 and the charging duration is about 80 μs with 1-μF bootstrap capacitor.

An Integrated Bootstrap Diode Emulator for 600-V High Voltage Gate Drive IC With P-Sub/P-Epi Technology

The failure mechanisms for two kinds of the 750-V Superjunction VDMOS (SJ-VDMOS) devices with different charge imbalance conditions (Qp Qn) under unclamped inductive switching (UIS) condition are investigated in detail by experiments and 2-D devices simulations in this paper. For Qp Qn. Not only the channel current but also the avalanche current caused by ON-state breakdown appears during the UIS turn-off process until the gate voltage decreases below the threshold voltage in the SJ-VDMOS device. The avalanche current flows beneath the n+ region and leads to the activation of the parasitic transistor.

Jing Zhu

Papers

Novel Snapback-Free Reverse-Conducting SOI-LIGBT With Dual Embedded Diodes

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

Isolation structure of high-voltage driving circuit

An Integrated Bootstrap Diode Emulator for 600-V High Voltage Gate Drive IC With P-Sub/P-Epi Technology

Failure Analysis of Superjunction VDMOS Under UIS Condition