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John H. Magerlein

Researcher at IBM

Publications -  51
Citations -  2039

John H. Magerlein is an academic researcher from IBM. The author has contributed to research in topics: Microchannel & Layer (electronics). The author has an hindex of 22, co-authored 51 publications receiving 1935 citations. Previous affiliations of John H. Magerlein include Veeco & GlobalFoundries.

Papers
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Multiple threads and parallel challenges for large simulations to accelerate a general Navier–Stokes CFD code on massively parallel systems

TL;DR: This paper proposes and analyze optimizations necessary to run CFD simulations consisting of multibillion‐cell mesh models on large processor systems, and describes two parallel strategies of an algebraic multigrid solver and details how to introduce new levels of parallelism based on compiler directives with OpenMP, transactional memory and thread level speculation.

IBM Research Report MEMS Fabrications for Wireless Communications Using Copper Interconnect Technology

Abstract: Wireless communications technology is growing and becoming a key segment of the semiconductor industry. One potential technology advancement is the miniaturization and integration of the passive components that currently make up 70% of the components in a cell phone and contribute to 80% of their costs [1]. Some of these passive components include inductors, variable capacitors, resonators, filters and switches. Integrating some or all of these passives on a single chip promises to introduce new designs of the wireless transceiver with added functionality so that multiple bands, multiple protocols, and internet connection can be handled by a single wireless device. Additional perceived benefits of integration on a single chip are increased performance, lower power consumption, and lower cost. This paper reviews the application of electrochemical processing to the fabrication of miniaturized integrated passive and MEMS devices.
Patent

Integrated circuit inductor of high q factor (q value)

TL;DR: In this paper, the authors proposed a method of forming the inductor, which consists of a step for providing a semiconductor substrate, another step for forming a dielectric layer on the surface of the substrate, and a third step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor.
Patent

Local reduction in layer thickness of compliant thermally conductive material on chip

TL;DR: In this article, the authors proposed to reduce the temperature of a hot spot of a chip by locally reducing the layer thickness of a compliant thermally conductive material on the chip.