Jose Ortiz Gonzalez

TL;DR: In this paper, a 2D finite element model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs.

TL;DR: The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates and shows that solutions are less effective for SiC-MOSFETs.

TL;DR: The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFs, cascode-driven WBG Fets, silicon NPT and Field-stop IGBTs, silicon super-junction MOSfETs and enhancement mode GaN high electron mobility transistors (HEMTs).

TL;DR: In this paper, the authors examined dynamic temperature-sensitive electrical parameters (TSEPs) for SiC MOSFETs and showed that the switching rate of the output current coupled with the gate current plateau (I GP) during turn-ON could be an effective TSEP under specific operating conditions.

TL;DR: In this article, the tradeoff between the switching energy and electrothermal robustness is explored for 1.2kV SiC MOSFET, silicon power MOS-FET and 900-V CoolMOS body diodes at different temperatures.