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Proceedings ArticleDOI

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

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TLDR
In this paper, a CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub y/H/sub z/, respectively.
Abstract
Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

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Proceedings ArticleDOI

Reliability challenges for 45nm and beyond

TL;DR: Interconnect RC time-delay worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects, and the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.
Patent

Topography reduction and control by selective accelerator removal

TL;DR: In this paper, a plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity) cavity, and then plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide feature metal protrusion over the metal-filled wide-feature cavity is higher than the height over field regions.
Journal ArticleDOI

Electromigration challenges for advanced on-chip Cu interconnects

TL;DR: To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration to enable overall EM reliability and optimized performance.
Journal ArticleDOI

Reliability of copper low-k interconnects

TL;DR: In this paper, the authors review some aspects of novel metallization schemes and tight-pitch copper/low-k interconnects from a reliability standpoint, based on recent understanding.
References
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Journal ArticleDOI

Electromigration in metals

TL;DR: In this article, an overview on the current understanding of electromigration in metals is provided. But the discussion is focused on studies in bulk metals and alloys and not on the studies in metallic thin films.
Journal ArticleDOI

Copper Metallization for High Performance Silicon Technology

TL;DR: In this article, the authors describe the development of an electroplating process for the copper network, dual-damascence chem-mech polishing (CMP), and effective liner material for copper diffusion barrier and adhesion promotion.
Journal ArticleDOI

Reduced electromigration of Cu wires by surface coating

TL;DR: In this article, a 10-20 nm thick metal cap was proposed to improve the lifetime of on-chip Cu damascene lines by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure.
Journal ArticleDOI

Electromigration reliability issues in dual-damascene Cu interconnections

TL;DR: The study of dual-damascene Cu has demonstrated the importance of statistics in analyzing EM reliability and has shown statistical evidence of bimodal failure behavior consistent with the presence of a weak and strong failure mode.
Journal ArticleDOI

Self-diffusion in pure metals☆

TL;DR: In this paper, the authors developed the equations that relate defect properties to measurable diffusion parameters for use in this and the following papers and demonstrated the potential errors inherent in relating high-temperature diffusion data over a limited temperature range to properties of monovacancies.
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