Showing papers by "Jun Fan published in 2001"

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Abstract: Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

DC power-bus modeling and design with a mixed-potential integral-equation formulation and circuit extraction

Abstract: The application of a circuit extraction approach based on a mixed-potential integral equation formulation (CEMPIE) for DC power-bus modeling in high-speed digital designs is detailed. Agreement with measurements demonstrates the effectiveness of the approach. Dielectric losses are included into the calculation of the Green's functions, and thus, incorporated into the rigorous first principles formulation. A SPICE model is then extracted from the discretized integral equation. A quasistatic approximation is used for the Green's functions to keep the extracted circuit elements frequency independent. Previous work has established a necessary meshing criterion in order to ensure accuracy for a given substrate thickness and dielectric constant to a desired frequency. Several power-bus design issues, such as surface mount decoupling and power-plane segmentation, were investigated using the modeling approach. The results and discussions illustrate the application of the method to DC power-bus design for printed circuit and multi-chip module substrates.

Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation

Abstract: The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design.

DC power bus noise isolation with power islands

Abstract: Segmented power planes are often used for DC power bus noise isolation in multi-layered printed circuit board (PCB) designs. To achieve a desirable noise isolation, different power plane segmentations can be used. A suitable modeling approach, as well as measurements, were employed to study the power bus isolation with several power plane segmentation configurations. The studied geometries included power island designs connected with a conducting bridge, a ferrite bead, and a /spl pi/-filter. In addition, different conducting bridge widths and power island gap widths were analyzed, and compared. The modeled and measured results show that power plane segmentations with proper designs can result in significant power bus noise isolation.

Including SMT ferrite beads in DC power bus and high-speed I/O line modeling

Abstract: Surface mount technology (SMT) ferrite beads are often used in high-speed digital circuit designs to mitigate noise. The common modeling approach is to include SMT ferrite beads as equivalent lumped LCR circuits. The work presented in this paper included SMT ferrite beads as a frequency-dependent impedance in a PEEC-like modeling tool denoted CEMPIE, a circuit extraction approach based on a mixed-potential integral equation formulation. Agreement with measurements demonstrates the approach. The applications shown are segmentation of power areas for noise isolation, and I/O line filtering.

The effects of via transitions on differential signals

Abstract: Vias in differential transmission lines have been modeled using the finite-difference time-domain (FDTD) method. The velocity that the differential signal propagated through the vias was estimated. Differential S-parameters were calculated up to 50 GHz. Below 10 GHz, the differential signal can propagate through vias without much reflection and distortion. However, as frequency increases, the reflection from the vias and the loss of differential power become significant.

Common-mode current harmonics on differential pair cable shields operating in a regime as high as 2.125 Gb/s

Abstract: The spectral harmonics of common-mode currents induced on high-speed differential cables operating at 1.0625 and 2.125 Gb/s were investigated using an analytical model and an experiment. Modeling of a differential clock type signal using waveforms with exponential rise and fall and adjustable delay skew and duty cycle allowed prediction of the spectral content of the resulting common-mode voltage waveform. A shielded test board was constructed to allow generation of a differential signal with selectable amounts of delay skew. Using an IC driver on the board as a differential source, common-mode current was measured at the source end of a long cable that was at the far end for both the differential and the common-modes. Modeled and measured results show that the fundamental frequency of the clock type waveform and the higher harmonics increase with increasing delay skew.

Evaluation of SMT decoupling design in a functioning high-speed PCB

Abstract: SMT decoupling capacitor location in DC power bus design is a critical design choice. Experimental evaluation of SMT decoupling design is presented in this work for a functioning high-speed PCB transmitting 1.0625 Gb/s serial data. SMT decoupling capacitors were removed in several steps while the swept-frequency |S/sub 21/| and power bus noise were monitored. It was found that the SMT decoupling capacitors located in proximity to the test ports decreased |S/sub 21/| and power bus noise at high frequencies, even far above their series resonant frequency. The hardware measurements demonstrate that local decoupling can be beneficial for high-frequency noise mitigation.

Modeling shared-via decoupling in a multi-layer structure using the CEMPIE approach

Abstract: The CEMPIE approach, a circuit extraction technique based on a mixed-potential integral equation, has been applied to model multi-layer structures including power and signal layers. Power-bus noise mitigation effects due to a decoupling capacitor were studied for several cases with different spacing between the capacitor and an integrated circuit (IC). Modeling results indicate that the capacitor sharing a common via with the IC power/ground pins is superior; viz., it results in the lowest power-bus noise under similar conditions.