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Showing papers by "Karl Opsomer published in 2016"


Journal ArticleDOI
TL;DR: The void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing shows that ruthenium can be used as a barrierless metallization in interconnects.
Abstract: Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 A of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.

74 citations


Journal ArticleDOI
TL;DR: In this article, the energy barrier for electrons between the Fermi level of Pt and the conduction band of several oxide insulators (SiO2, Al2O3, HfO2 and Hf0.8Al0.2Ox, Sr0.53Ti0.47O3) was determined by using internal photoemission of electrons.
Abstract: Thanks to its good thermal stability, including resistance to oxidation, platinum (Pt) is widely used in prototyping a wide spectrum of electron devices ranging from metal-oxide-semiconductor (MOS) transistors to resistive switching memory cells. In this work, the energy barriers for electrons between the Fermi level of Pt and the conduction band of several oxide insulators (SiO2, Al2O3, HfO2, Hf0.8Al0.2Ox, Sr0.53Ti0.47O3) were determined by using internal photoemission of electrons. By combining this barrier value with the electron affinity of the particular oxide, the effective work function (EWF) of Pt was determined for different interfaces. As studied over the reference Pt/oxide/Si stacks de-gassed in high vacuum at 400 °C, the EWF of Pt is found to differ significantly from the accepted vacuum WF value of 5.6 eV. The EWF is equal to 5.2 eV at the Pt/Al2O3 interface, 5.1 eV at Pt/HfO2, 5.3 eV at Pt/Hf0.8Al0.2Ox, 4.8 eV at Pt/SiO2, and 5.8 eV at the Pt/Sr0.53Ti0.47O3 interface indicating the presence of a polarization layer of which the contribution to the EWF depends on the oxide composition. Furthermore, annealing in H2 at 400 °C reduces the Pt EWF by ∼0.5 eV at all interfaces except for the Pt/Sr0.53Ti0.47O3 one. This observation indicates the formation of an additional H-related dipole at the Pt/oxide interfaces and suggests that the vacuum WF of Pt cannot be used as the value relevant for the MOS properties.

5 citations


Journal ArticleDOI
TL;DR: In this article, the authors demonstrate a thermally stable copper supply layer by Si alloying of Cu0.6Te0.4 for application in conductive bridge random access memory (CBAM) cells.
Abstract: In this work we demonstrate a thermally stable copper supply layer by Si alloying of Cu0.6Te0.4 for application in Conductive Bridge Random Access Memory (CBRAM) cells. A good thermal stability of the copper supply layer is necessary to allow its implementation in future memory devices. In situ X-ray diffraction is used to investigate the crystallization behaviour of Cu0.6Te0.4 layers with Si contents up to 20 at%. Low Si concentrations result in crystallization, phase separation and transformations at temperatures below 400 °C, whereas addition of 20 at% Si results in a layer that remains amorphous up to temperatures exceeding 500 °C, making it compatible with back end of line temperatures. Moreover, atomic force microscopy measurements show a very smooth surface morphology up to temperatures exceeding 400 °C. The absence of grain boundaries in the amorphous layer is expected to contribute to the uniformity of the supply layer, and hence it should be beneficial for integration in scaled devices. We attribute the good ability of Si to keep the material amorphous to the high coordination number of Si and the formation of strong bonds which are difficult to break, making rearrangement in a lattice more difficult to proceed. This is further evidenced by XPS measurements, which suggest the occurrence of both Si–Si and Si–Te bonds. CBRAM functionality of this composition is demonstrated by integrating the material in 580 μm diameter dot Pt/Cu–Te–Si/Al2O3/n+ Si CBRAM cells.

3 citations