The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Channel semiconductor alloy layer growth adjusted by impurity ion implantation

During many decades, Moore's law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry predict and structure its future growth and organize its research focuses in a more visible and synergetic way. Simultaneously, the continuous growth of global demand with respect to semiconductor products (connectivity, security, healthcare, energy, entertainment, etc.) spanned a larger field where the impact of Moore's law could be observed. The scaling of electronic devices is facing today several physical and economic obstacles, including the difficulty of adapting lithography tools, maintaining good device performance and ensuring a reliable design with the continuously shrinking device features. Several solutions have been proposed at both manufacturing and system levels in order to address this situation. Some emerging technologies based on quasi one- and zero-dimensional structures are promising candidates to succeed complementary metal-oxide-semiconductor (CMOS) technology. These technologies, for instance silicon nanowires (SiNWs) and carbon nanotubes (CNTs), share some aspects, including high variability and regular organization. The assessment of their benefits requires an interdisciplinary approach, so that technological challenges and opportunities can be leveraged at the design level. This dissertation is a new interdisciplinary vision in the field of emerging technologies. The work in this thesis is done at three levels. At the technology level, a novel fabrication technique for silicon nanowire crossbars is demonstrated, whereby the goal is to show the ability to use CMOS-compatible and only standard photolithography steps in order to achieve a sub-lithographic pitch. At the system level, the crossbar decoder design is optimized by developing new families of encoding schemes, which enhance the decoder fault-tolerance and save area. A testing procedure for this circuit part is also developed, aiming at the introduction of a novel concept of design for test in nanowire crossbar technologies. At the logic design level, the ambipolarity of carbon nanotube field effect transistors (CNTFETs) is leveraged by designing a novel library of CNTFET logic gates, which are used in logic synthesis, proving the higher expressive power and compactness of CNTFET technology compared with CMOS.

Fabrication and design of nanoscale regular circuits

Synthesis of Tm2O3-doped Lu2O3 nanoparticle using homogeneous co-precipitation method along with its material/optical characterization is reported. Four different compositions with variation of Tm: Lu ratios are synthesized followed by calcination at different temperatures (800, 1000 and 1200 °C) was performed to optimize the synthesis process as well as composition. The XRD analysis indicates steady growth of particle size with increasing calcination temperature and an average particle size of 100 nm was achieved at 1200 °C. Pure bixbyite structure was observed for every sample independent of Tm: Lu ratio. The FESEM and HRTEM analysis associated with EDX indicates formation of pure crystalline particles and results are in good agreement with XRD analysis. The photoluminescence spectra observed under 808 nm excitation exhibit characteristic Tm emission peak that extended beyond 2 micron region the intensity of which is strongly depends on Lu: Tm ratio as well as calcination temperature. The overall result reveals that the synthesized material which indicates good thermal stability is a potential doping material for the development of Thulium-doped fiber suitable for eye-safe laser application.

Synthesis and characterization of Tm2O3-doped Lu2O3 nanoparticle suitable for fabrication of thulium-doped laser fiber

Microelectronics advancements have made possible monolithic ASIC realizations to support new modulation formats on fiber such as QPSK Critical aspects of high-speed ADC/DAC and DSP techniques are discussed for implementations at 40Gb/s and beyond

Microelectronics advancements to support new modulation formats and DSP techniques

The successful era of CMOS technology is coming to an end. The limit on minimum fabrication dimensions of transistors and the increasing leakage power hinder the technological scaling that has characterized the last decades. In several different ways, this problem has been addressed changing the architectures implemented in CMOS, adopting parallel processors and thus increasing the throughput at the same operating frequency. However, architectural alternatives cannot be the definitive answer to a continuous increase in performance dictated by Moore's law. This problem must be addressed from a technological point of view. Several alternative technologies that could substitute CMOS in next years are currently under study. Among them, magnetic technologies such as NanoMagnet Logic (NML) are interesting because they do not dissipate any leakage power. More- over, magnets have memory capability, so it is possible to merge logic and memory in the same device. However, magnetic circuits, and NML in this specific research, have also some important drawbacks that need to be addressed: first, the circuit clock frequency is limited to 100 MHz, to avoid errors in data propagation; second, there is a connection between circuit layout and timing, and in particular, longer wires will have longer latency. These drawbacks are intrinsic to the technology and for this reason they cannot be avoided. The only chance is to limit their impact from an architectural point of view. The first step followed in the research path of this thesis is indeed the choice and optimization of architectures able to deal with the problems of NML. Systolic Ar- rays are identified as an ideal solution for this technology, because they are regular structures with local interconnections that limit the long latency of wires; more- over they are composed of several Processing Elements that work in parallel, thus exploit parallelization to increase throughput (limiting the impact of the low clock frequency). Through the analysis of Systolic Arrays for NML, several possible im- provements have been identified and addressed: 1) it has been defined a rigorous way to increase throughput with interleaving, providing equations that allow to esti- mate the number of operations to be interleaved and the rules to provide inputs; 2) a latency insensitive circuit has been designed, that exploits a data communication protocol between processing elements to avoid data synchronization problems. This feature has been exploited to design a latency insensitive Systolic Array that is able to execute the Floyd-Steinberg dithering algorithm. All the improvements presented in this framework apply to Systolic Arrays implemented in any technology. So, they can also be exploited to increase performance of today's CMOS parallel circuits. This research path is presented in Chapter 3. While Systolic Arrays are an interesting solution for NML, their usage could be quite limited because they are normally application-specific. The second re- search path addresses this problem. A Reconfigurable Systolic Array is presented, that can be programmed to execute several algorithms. This architecture has been tested implementing many algorithms, including FIR and IIR filters, Discrete Cosine Transform and Matrix Multiplication. This research path is presented in Chapter 4. In common Von Neumann architectures, the logic part of the circuit and the memory one are separated. Today bus communication between logic and memory represents the bottleneck of the system. This problem is addressed presenting Logic- In-Memory (LIM), an architecture where memory elements are merged in logic ones. This research path aims at defining a real LIM architectures. This has been done in two steps. The first step is represented by an architecture composed of three layers: memory, routing and logic. In the second step instead the routing plane is no more present, and its fea

Architectural Solutions for NanoMagnet Logic

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite carbon, HiK,...), Si based CMOS will be scaled beyond the ITRS as the future system-on-chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, wi ll bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance w ll be the major challenges in the future.

NanoCMOS devices at the end and beyond the roadmap

Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. Multigate architectures allow to increase devices drivability, reduce power, new memory devices opportunities and will be necessary to develop future applications. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (HiK, Ge, diamond/graphite Carbon,...), Si based CMOS will be scaled beyond the ITRS as the system-on-chip platform

CMOS devices architectures for the end of the roadmap and beyond

The scaling of some today's high mobility MOSFETs solutions was discussed. The enhancement (between 10-25% for sub-40nm devices) is often lower than the natural mobility decrease due to high short-channel doping (for bulk) or border S/D effects (on SOI). Further understanding of the short channel scattering effects is necessary to engineer next generation high mobility channels

High Mobility Nano-Scaled CMOS: Some Opportunities and Challenges

Since 1994, the International Technology Roadmap for Semiconductor (ITRS)[1] has been accelerating the scaling of CMOS devices to lower dimensions despite the difficulties that appear in device optimization at the sub 10nm level[2][3][4][5](Fig.1). Breakthroughs are required to continue scaling at the same rate. Which are the main showstoppers for CMOS scaling? Short channel effects and tunneling in the gate dielectric are at the origin of the showstoppers. Channel, gate stack and source and drain engineering have to be reconsidered for new devices architecture optimization. The eventual combination FD SOI (single or multi gateMOSFETs[6],[7],[8])(Figs.2, 3 and 4) and strained dual channels [4],[5],[9],[10] will allow new solutions to enhance the Ion/ Ioff trade of future low cost System On Chip(SOC) design[4][7]. Metal gates [11] show promising perspectives to avoid gate dopant depletion. The issue of electron mobility degradation in the channel of HiK isolated MOSFETs will require innovative solutions to be introduced[12](Fig. 5). Supply voltages lower than 1V will require FDSOI architectures and threshold voltage adjust by tuning the gate material workfunction. Laser or Flash Annealing, Plasma Doping will be required to minimize parasitic effects. It will be very difficult for alternative devices to compete with CMOS logic because of the low series resistance required[13]. Due to the important charge retention capabilities, trapping phenomena in Silicon Nanocrystals are exploited for Flash memory applications[14](Fig. 6). By introducing new materials, i.e. GeOI[16] (Fig.7) or Diamond Carbon [17](Fig.8), Si based CMOS will scale beyond the ITRS[1] as the future SOC Platform allowing the integration of new disruptive devices. Single Electronics and Power Consumption reduction will be major research subjects in the next decades[17].

L. Clavelier

Papers

NanoCMOS devices at the end and beyond the roadmap

CMOS devices architectures for the end of the roadmap and beyond

High Mobility Nano-Scaled CMOS: Some Opportunities and Challenges

Nanoelectronics devices for the end of the roadmap and beyond