L
L.F. Tiemeijer
Researcher at Philips
Publications - 34
Citations - 1489
L.F. Tiemeijer is an academic researcher from Philips. The author has contributed to research in topics: CMOS & Noise (electronics). The author has an hindex of 17, co-authored 34 publications receiving 1439 citations.
Papers
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Journal ArticleDOI
Noise modeling for RF CMOS circuit simulation
A.J. Scholten,L.F. Tiemeijer,R. van Langevelde,R.J. Havens,A.T.A. Zegers-van Duijnhoven,V. C. Venezia +5 more
TL;DR: In this paper, a nonquasi-static channel segmentation model was proposed to predict both drain and gate current noise in 0.18-/spl mu/m CMOS technology.
Journal ArticleDOI
RF-CMOS performance trends
Pierre H. Woerlee,M.J. Knitel,R. van Langevelde,D.B.M. Klaassen,L.F. Tiemeijer,A.J. Scholten,A.T.A. Zegers-van Duijnhoven +6 more
TL;DR: In this paper, the impact of scaling on the analog performance of MOS devices at RF frequencies was studied and a scaling methodology for RF-CMOS based on limited linearity degradation was proposed.
Journal ArticleDOI
A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors
L.F. Tiemeijer,R.J. Havens +1 more
TL;DR: In this article, a new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the deembedded figures of merit.
Journal ArticleDOI
Comparison of the "pad-open-short" and "open-short-load" deembedding techniques for accurate on-wafer RF characterization of high-quality passives
TL;DR: In this paper, the impedance errors remaining after applying the industry standard "open short," a "pad-open-short," and a "Open Shortload" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz.
Journal ArticleDOI
RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics
TL;DR: In this article, the authors present a MOS Capacitance-Voltage measurement methodology that is robust against gate leakage current densities up to 1000 A/cm/sup 2.