L
Lars Hedrich
Researcher at Goethe University Frankfurt
Publications - 73
Citations - 1015
Lars Hedrich is an academic researcher from Goethe University Frankfurt. The author has contributed to research in topics: Formal verification & State space. The author has an hindex of 17, co-authored 72 publications receiving 928 citations. Previous affiliations of Lars Hedrich include Leibniz University of Hanover & Hanover College.
Papers
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Proceedings ArticleDOI
Design and architectures for dependable embedded systems
Jorg Henkel,Lars Bauer,Joachim Becker,Oliver Bringmann,Uwe Brinkschulte,Samarjit Chakraborty,Michael Engel,Rolf Ernst,Hermann Härtig,Lars Hedrich,Andreas Herkersdorf,Rüdiger Kapitza,Daniel Lohmann,Peter Marwedel,Marco Platzner,Wolfgang Rosenstiel,Ulf Schlichtmann,Olaf Spinczyk,Mehdi B. Tahoori,Jürgen Teich,Norbert Wehn,Hans-Joachim Wunderlich +21 more
TL;DR: An overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years is presented, including a new classification on faults, errors, and failures.
Proceedings ArticleDOI
Model checking algorithms for analog verification
TL;DR: This contribution presents the first method for model checking on nonlinear analog systems, based on digital CTL model checking algorithms and results in hybrid model checking, and an extension to the CTL language is needed.
Journal ArticleDOI
FEATS: Framework for Explorative Analog Topology Synthesis
Markus Meissner,Lars Hedrich +1 more
TL;DR: An isomorphism algorithm is developed, which reduces a given set of circuits to its unique being one of the first methodologies addressing this issue and demonstrating the claimed feasibility and applicability of the synthesis framework in general and in the context of system design.
Book ChapterDOI
Formal Verification for Nonlinear Analog Systems: Approaches to Model and Equivalence Checking
TL;DR: In this article, equivalence and model checking methods for nonlinear analog systems are presented based on the system's nonlinear state space description, where the equivalence checker computes a nonlinear transformation of the state space descriptions into a canonical form.
Proceedings ArticleDOI
A formal approach to nonlinear analog circuit verification
Lars Hedrich,Erich Barke +1 more
TL;DR: This paper presents an approach to nonlinear dynamic analog circuit verification by comparing the implicit nonlinear state space descriptions of the two systems on the same or on different levels of abstraction by sampling the state spaces and by building a nonlinear one-to-one mapping of the state Spaces.