Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO 2 in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO 2 emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high- k materials.

Development of hafnium based high-k materials—A review

The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

Advanced high-κ dielectric stacks with polySi and metal gates: recent progress and current challenges

High- κ gate dielectrics like HfO 2 and HfSiO(N) are considered for the replacement of SiO 2 and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap for Semiconductors. However, major problems remain to be solved before the possible use of high- κ gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high- κ -based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high- κ gate dielectric appears to be a promising solution for the further scaling down of CMOS devices.

Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.

Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and chemical characteristics of metal-oxide semiconductor field-effect transistors (MOSFETs) prepared by low-thermal-budget (∼600 °C) NH3 post-deposition annealing of HfSiON gate dielectric have been investigated. Compared to control Hf-silicate, HfSiON showed excellent thickness scalability, low leakage current density (J), and superior thermal stability. With proper annealing-time optimization, effective oxide thickness as low as 9.2 A with J<100 mA/cm2 at gate voltage Vg=−1.5 V has been achieved. C–V hysteresis of HfSiON MOSFET was found to be small (<20 mV). Unlike NH3 surface nitridation (NH3 pre-treatment prior to Hf-silicate deposition), no degradation in Gm (transconductance), Id–Vg (drain current–gate voltage), or Id–Vd (drain current–drain voltage) characteristics has been observed.

High-performance TaN/HfSiON/Si metal-oxide-semiconductor structures prepared by NH3 post-deposition anneal

The electrical, material, and reliability characteristics of zirconium oxynitride (Zr-oxynitride) gate dielectrics were evaluated. The nitrogen (/spl sim/1.7%) in Zr-oxynitride was primarily located at the Zr-oxynitride/Si interface and helped to preserve the composition of the nitrogen-doped Zr-silicate interfacial layer (IL) during annealing as compared to the ZrO/sub 2/ IL - resulting in improved thermal stability of the Zr-oxynitride. In addition, the Zr-oxynitride demonstrated a higher crystallization temperature (/spl sim/600/spl deg/C) as compared to ZrO/sub 2/ (/spl sim/400/spl deg/C). Reliability characterization was performed after TaN-gated nMOSFET fabrication of Zr-oxynitride and ZrO/sub 2/ devices with equivalent oxide thickness (EOTs) of 10.3 /spl Aring/ and 13.8 /spl Aring/, respectively. Time-zero dielectric breakdown and time-dependent dielectric breakdown (TDDB) characteristics revealed higher dielectric strength and effective breakdown field for the Zr-oxynitride. High-temperature forming gas (HTFG) annealing on TaN/Zr-oxynitride nMOSFETs with an EOT of 11.6 /spl Aring/ demonstrated reduced D/sub it/, which resulted in reduced swing (69 mV/decade), reduced off-state leakage current, higher transconductance, and higher mobility. The peak mobility was increased by almost fourfold from 97 cm/sup 2//V/spl middot/s to 383 cm/sup 2//V/spl middot/s after 600/spl deg/C HTFG annealing.

Electrical characterization and material evaluation of zirconium oxynitride gate dielectric in TaN-gated NMOSFETs with high-temperature forming gas annealing

Breakdown voltage distribution, Weibull slopes, and area scaling factors have been investigated for HfO/sub 2/ gate dielectrics in order to gain a better understanding of the breakdown mechanism. Weibull slope of thick HfO/sub 2/ (e.g., /spl beta//spl ap/4 for EOT=2.5 nm) is smaller than that of SiO/sub 2/ with similar physical thickness, whereas /spl beta/ of the thinner HfO/sub 2/ (e.g., /spl beta//spl ap/2 for EOT=1.4 nm) is similar to that of SiO/sub 2/. The implication of the thickness dependence of /spl beta/ is discussed.

M.S. Akbar

Papers

Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

High-performance TaN/HfSiON/Si metal-oxide-semiconductor structures prepared by NH3 post-deposition anneal

Electrical characterization and material evaluation of zirconium oxynitride gate dielectric in TaN-gated NMOSFETs with high-temperature forming gas annealing

Thickness dependence of Weibull slopes of HfO 2 gate dielectrics