There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

/pdf/high-k-materials-and-metal-gates-for-cmos-applications-4hs77i3c4a.pdf

High-K materials and metal gates for CMOS applications

https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/ƒ noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in small devices.

NBTI from the perspective of defect states with widely distributed time scales

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$ -FinFETs

This paper reviews some of the recent learning at IMEC in reliability research on high-k gate stacks. We show how measurement, characterization techniques and physical degradation models can be transferred from SiO2 (or SiON) single layers to SiO2(SiON)/high-k stacks. In a first part, negative bias temperature instability (NBTI) is discussed. We show how interface states created at the SiO2 (or SiON)/substrate interface determine to a large extend the NBTI. Nitridation has a strong negative impact on NBTI, while thickness or composition of the high-k layer have nearly no influence. In a second part, we discuss the effect of bulk traps in the high-k layer. These traps cause fast Vt-instability and hysteresis, as well as significant positive bias temperature instability (PBTI). Additional bulk traps are created under electrical stress and form percolating paths of two or more traps causing soft breakdown (SBD). At low voltage and with metal gates, the SBD-leakage path develops into a hard breakdown (HBD) after some further wear-out time. We summarize the methodology to come to a complete reliability prediction that includes multiple SBDs and HBD. In high-k stacks, the leakage current increase due to multiple SBDs can be a reliability threat for some applications.

Review of reliability issues in high-k/metal gate stacks

In this letter, we demonstrate a one-transistor capacitorless DRAM on standard bulk FinFET, using no additional processing. It is shown that, due to the use of the ground-plane doping and optimization of the READ bias conditions, no special process adjustment is required to obtain wide programming windows and long retention times, even for fin widths down to 20 nm.

Marc Aoulaiche

Papers

NBTI from the perspective of defect states with widely distributed time scales

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$ -FinFETs

Review of reliability issues in high-k/metal gate stacks

Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell