This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

/pdf/toward-nanowire-electronics-2ea30585ug.pdf

Toward Nanowire Electronics

In the present article we will discuss the electronic trans- port properties of carbon nanotube field-effect transistors (CNFETs) Three different device concepts will be studied in more detail: Schottky-barrier CNFETs with metallic source and drain contacts, conventional-type CNFETs with doped nanotube segments as source and drain electrodes and finally a new concept, the tunneling CNFET As it turns out, tunneling phenomena play a prominent role in all three CNFET designs and determine their electrical behavior to a large extend In addition, the one-dimensionality of the electronic transport makes them ideally suited for novel device architecture such as the tunneling CNFET Analytical as well as simulation results will be given and compared with each other and with experimental data in order to explain the different influences on the electronic transport in CNFETs and thus on the device behavior (© 2008 WILEY-VCH Verlag GmbH & Co KGaA, Weinheim)

/pdf/tunneling-phenomena-in-carbon-nanotube-field-effect-3b6pi4zs6v.pdf

Tunneling phenomena in carbon nanotube field‐effect transistors

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

https://science.sciencemag.org/content/sci/361/6400/387.full.pdf

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

/pdf/fabrication-and-characterization-of-the-charge-plasma-diode-57ysyamz4p.pdf

Fabrication and Characterization of the Charge-Plasma Diode

As Moore's law approaches its end, two-dimensional (2D) materials are intensely studied for their potentials as one of the ``More than Moore' (MM) devices. However, the ultimate performance limits and the optimal design parameters for such devices are still unknown. One common problem for the 2D-material-based device is the relative weak on-current. In this study, two-dimensional Schottky-barrier field-effect transistors (SBFETs) consisting of in-plane heterojunctions of 1T metallic-phase and 2H semiconducting-phase transition-metal dichalcogenides (TMDs) are studied following the recent experimental synthesis of such devices at a much larger scale. Our ab initio simulation reveals the ultimate performance limits of such devices and offers suggestions for better TMD materials. Our study shows that the Schottky-barrier heights (SBHs) of the in-plane 1T/2H contacts are smaller than the SBHs of out-of-plane contacts, and the contact coupling is also stronger in the in-plane contact. Due to the atomic thickness of the monolayer TMD, the average subthreshold swing of the in-plane TMD-SBFETs is found to be close to the limit of 60 mV/dec, and smaller than that of the out-of-plane TMD-SBFET device. Different TMDs are considered and it is found that the in-plane $\mathrm{WT}{\mathrm{e}}_{2}\text{\ensuremath{-}}\mathrm{SBFET}$ provides the best performance and can satisfy the performance requirement of the sub-10-nm high-performance transistor outlined by the International Technology Roadmap for Semiconductors, and thus could be developed into a viable sub-10-nm MM device in the future.

https://link.aps.org/accepted/10.1103/PhysRevB.96.165402

In-plane Schottky-barrier field-effect transistors based on 1 T /2 H heterojunctions of transition-metal dichalcogenides

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage Vth of SOI SB-MOSFETs and find a nonmonotonic behavior of Vth. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be ~ 3 nm

/pdf/on-the-performance-of-single-gated-ultrathin-body-soi-1jbtx7z6yd.pdf

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The impact of the gate oxide and the silicon-on-insulator (SOI) body thickness on the electrical performance of SOI Schottky-barrier (SB) MOSFETs with fully nickel silicided source and drain contacts is experimentally investigated. The subthreshold swing S is extracted from the experimental data and serves as a measure for the carrier injection through the SBs. It is shown that decreasing the gate oxide and body thickness allows to strongly increase the carrier injection and hence, a significantly improved on-state of SB-MOSFETs can be obtained

/pdf/improved-carrier-injection-in-ultrathin-body-soi-schottky-1pbu72t1p2.pdf

Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height PhiB is found to strongly affect the threshold voltage Vth of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness tOX and SOI body thickness; the contribution of inhomogeneity to the Vth variation becomes less pronounced with smaller tOX and/or larger tsi . Moreover, an enhanced Vth variation is observed for devices with dopant segregation used for reduction of the effective PhiB . Furthermore, a multigate structure is found to help suppress the Vth variation by improving carrier injection through reduction of its sensitivity to the PhiB inhomogeneity. A new method for extraction of PhiB from room temperature transfer characteristics is also presented.

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

Schottky barrier height engineering by silicidation induced impurity segregation is demonstrated. The segregation of sulfur at the NiSi/Si interface leads to a gradual decrease of the SBH on n-Si(100) from 0.65 eV to 0.07 eV, and correspondingly, to an increase of the SBH on p-Si(100). Alternatively, the effective SBH of NiSi is reduced by As and B segregation during silicidation. Using these techniques, SB-MOSFETs were fabricated. The transistors with impurity segregation at source/drain to the silicon channel show significant performance improvements

Tuning of Schottky barrier heights by silicidation induced impurity segregation

In this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S194642740008667X

Min Zhang

Papers

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

Tuning of Schottky barrier heights by silicidation induced impurity segregation

Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI