Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

/pdf/differential-power-analysis-4t7fjmuc7b.pdf

Differential Power Analysis

This monograph provides an overview of general deep learning methodology and its applications to a variety of signal and information processing tasks. The application areas are chosen with the following three criteria in mind: (1) expertise or knowledge of the authors; (2) the application areas that have already been transformed by the successful use of deep learning technology, such as speech recognition and computer vision; and (3) the application areas that have the potential to be impacted significantly by deep learning and that have been experiencing research growth, including natural language and text processing, information retrieval, and multimodal information processing empowered by multi-task deep learning.

/pdf/deep-learning-methods-and-applications-5cyi610sjz.pdf

Deep Learning: Methods and Applications

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

Recently, the hybrid deep neural network (DNN)- hidden Markov model (HMM) has been shown to significantly improve speech recognition performance over the conventional Gaussian mixture model (GMM)-HMM. The performance improvement is partially attributed to the ability of the DNN to model complex correlations in speech features. In this paper, we show that further error rate reduction can be obtained by using convolutional neural networks (CNNs). We first present a concise description of the basic CNN and explain how it can be used for speech recognition. We further propose a limited-weight-sharing scheme that can better model speech features. The special structure such as local connectivity, weight sharing, and pooling in CNNs exhibits some degree of invariance to small shifts of speech features along the frequency axis, which is important to deal with speaker and environment variations. Experimental results show that CNNs reduce the error rate by 6%-10% compared with DNNs on the TIMIT phone recognition and the voice search large vocabulary speech recognition tasks.

/pdf/convolutional-neural-networks-for-speech-recognition-59lskxzlgf.pdf

Convolutional neural networks for speech recognition

From the Publisher:
Connectionist Speech Recognition: A Hybrid Approach describes the theory and implementation of a method to incorporate neural network approaches into state-of-the-art continuous speech recognition systems based on Hidden Markov Models (HMMs) to improve their performance. In this framework, neural networks (and in particular, multilayer perceptrons or MLPs) have been restricted to well-defined subtasks of the whole system, i.e., HMM emission probability estimation and feature extraction. The book describes a successful five year international collaboration between the authors. The lessons learned form a case study that demonstrates how hybrid systems can be developed to combine neural networks with more traditional statistical approaches. The book illustrates both the advantages and limitations of neural networks in the framework of a statistical system. Using standard databases and comparing with some conventional approaches, it is shown that MLP probability estimation can improve recognition performance. Other approaches are discussed, though there is no such unequivocal experimental result for these methods. Connectionist Speech Recognition: A Hybrid Approach is of use to anyone intending to use neural networks for speech recognition or within the framework provided by an existing successful statistical approach. This includes research and development groups working in the field of speech recognition, both with standard and neural network approaches, as well as other pattern recognition and/or neural network researchers. This book is also suitable as a text for advanced courses on neural networks or speech processing.

Connectionist Speech Recognition: A Hybrid Approach

A new active-pull-down non-threshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate The circuit utilizes an APD-NMOS emitter-follower stage Simulation results based on 06-/spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 34/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV A comparison of critical-path delay has showed the superiority of the novel circuit over ECL circuits especially in the low-power region >

BiCMOS active-pull-down non-threshold logic circuits for high-speed low-power applications

In the previous chapter, the MTCMOS technique was used to reduce standby leakage power in combinational logic circuits, while attaining a sufficient performance. However, special attention must be paid to the MTCMOS design of sequential logic circuits such as latches and flip-flops (FFs) that have memory functions; this is necessary because stored data in the latch or FF circuits cannot be retained during the sleep standby mode because the virtual ground rails would be floating to cut off the leakage current. This would disconnect the storage nodes from the true power supply rails and possibly corrupt the stored data.

MTCMOS Sequential Circuits

This article presents a novel method for the design of broadband amplifiers in CMOS technology. The proposed design is based on equalizing the frequency response of NMOS transistors over the amplifier bandwidth. The compensating network is realized using passive elements available in CMOS technology. Simulation results indicate successful implementations of broadband amplifiers in 0.18 /spl mu/m CMOS with the bandwidth up to 30 GHz. The paper also reviews the design of broadband matching networks of the amplifier, completing the design process of broadband CMOS amplifiers.

https://ieeexplore.ieee.org/iel5/10009/32149/01496675.pdf

A systematic approach for design of broadband CMOS amplifiers

As the number of global interconnect buffers is expected to reach 700,000 in the 70nm CMOS process, their adverse impact on the chip total power consumption becomes evident. In this paper, we formulate the power optimal maze routing and buffer insertion/sizing problem for a two pin net, as a shortest paths ranking problem. The polynomial time bound on our formulation fits well within the context of the increased number of buffers. Moreover, its ability to account for buffer and wire blockage arising from the underlying blocks in today's SOC's is an advantage over the analytical alternative formulations. During the assessment of the impact of technology scaling using a set of MCNC benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.

POMR: a power-optimal maze routing methodology

In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will be studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, show an improvement of 64% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating in the low power regime (< 1 mW). Moreover, the BJT-MOS frequency divider configuration a high input sensitivity throughout the frequency range of operation. In addition, a proposed BiCMOS latched-comparator shows favorable input voltage sensitivity over conventional bipolar design under low-power operation. Secondly, a brief overview of high-performance ECL circuit techniques is covered along with a rough comparison and evaluation of such techniques. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.

Mohamed I. Elmasry

Papers

BiCMOS active-pull-down non-threshold logic circuits for high-speed low-power applications

MTCMOS Sequential Circuits

A systematic approach for design of broadband CMOS amplifiers

POMR: a power-optimal maze routing methodology

High-Performance CML, ECL and NTL Bicmos Circuits