Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

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Differential Power Analysis

This monograph provides an overview of general deep learning methodology and its applications to a variety of signal and information processing tasks. The application areas are chosen with the following three criteria in mind: (1) expertise or knowledge of the authors; (2) the application areas that have already been transformed by the successful use of deep learning technology, such as speech recognition and computer vision; and (3) the application areas that have the potential to be impacted significantly by deep learning and that have been experiencing research growth, including natural language and text processing, information retrieval, and multimodal information processing empowered by multi-task deep learning.

/pdf/deep-learning-methods-and-applications-5cyi610sjz.pdf

Deep Learning: Methods and Applications

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

Recently, the hybrid deep neural network (DNN)- hidden Markov model (HMM) has been shown to significantly improve speech recognition performance over the conventional Gaussian mixture model (GMM)-HMM. The performance improvement is partially attributed to the ability of the DNN to model complex correlations in speech features. In this paper, we show that further error rate reduction can be obtained by using convolutional neural networks (CNNs). We first present a concise description of the basic CNN and explain how it can be used for speech recognition. We further propose a limited-weight-sharing scheme that can better model speech features. The special structure such as local connectivity, weight sharing, and pooling in CNNs exhibits some degree of invariance to small shifts of speech features along the frequency axis, which is important to deal with speaker and environment variations. Experimental results show that CNNs reduce the error rate by 6%-10% compared with DNNs on the TIMIT phone recognition and the voice search large vocabulary speech recognition tasks.

/pdf/convolutional-neural-networks-for-speech-recognition-59lskxzlgf.pdf

Convolutional neural networks for speech recognition

From the Publisher:
Connectionist Speech Recognition: A Hybrid Approach describes the theory and implementation of a method to incorporate neural network approaches into state-of-the-art continuous speech recognition systems based on Hidden Markov Models (HMMs) to improve their performance. In this framework, neural networks (and in particular, multilayer perceptrons or MLPs) have been restricted to well-defined subtasks of the whole system, i.e., HMM emission probability estimation and feature extraction. The book describes a successful five year international collaboration between the authors. The lessons learned form a case study that demonstrates how hybrid systems can be developed to combine neural networks with more traditional statistical approaches. The book illustrates both the advantages and limitations of neural networks in the framework of a statistical system. Using standard databases and comparing with some conventional approaches, it is shown that MLP probability estimation can improve recognition performance. Other approaches are discussed, though there is no such unequivocal experimental result for these methods. Connectionist Speech Recognition: A Hybrid Approach is of use to anyone intending to use neural networks for speech recognition or within the framework provided by an existing successful statistical approach. This includes research and development groups working in the field of speech recognition, both with standard and neural network approaches, as well as other pattern recognition and/or neural network researchers. This book is also suitable as a text for advanced courses on neural networks or speech processing.

Connectionist Speech Recognition: A Hybrid Approach

In this paper, MOS current mode logic (MCML) is implemented in a multi-threshold CMOS technology. The design scheme allows the reduction of the minimum operational supply voltage, as well as the elimination of level shifters used. A high-speed 1:8 2.5 Gbit/s demultiplexer is used as a test vehicle. A 37% power saving is achieved. Furthermore, the impact of using the MTCMOS implementation over circuit parameters such as output impedance, current-matching-ratio, common-mode-rejection-ratio, gain, threshold voltage fluctuations and frequency response is investigated. This work is important for industry since the MTCMOS technique opens a new alley for reducing power in MCML high-speed implementations while attaining the required data rates.

Power reduction via an MTCMOS implementation of MOS current mode logic

An architectural synthesis methodology for a multibus multifunctional unit processor is presented. It is implemented as part of a design aid tool called SPAID. The input to SPAID is a DSP flow graph algorithm description with the required throughput and latency. The synthesized processor is a self-timed element externally, while it is internally synchronous and suitable for a systolic multiprocessor implementation for large DSP applications. For a benchmark elliptic filter algorithm SPAID synthesizes architectures with a linear topology that use fewer interconnects and multiplexers than other systems synthesizing random-topology architectures for the same throughput. >

http://ieeexplore.ieee.org/iel2/212/3483/00122459.pdf

Automatic synthesis of a multi-bus architecture for DSP

A new method, called DVDV, for low-power design of high-performance CMOS logic circuits is presented. DVDV utilizes a library of gates with dual supply voltages (V/sub dd/) and dual threshold voltages (V/sub th/) to achieve high-performance with minimum dynamic and leakage power. A Depth-First-Search (DFS) based heuristic for DVDV node assignment is described. Exercising the techniques on a set of benchmarks shows significant power savings over the dual-V, (with a single V/sub th/) scheme, and faster speeds than those possible with the dual-V/sub th/ (and a single V/sub dd/) approach.

Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach

A new circuit that generates low-frequency noise is presented. This circuit is based upon an electronic realization of the logistic map system. The noise power density spectrum of the output was measured and confirmed to be approximately white. We also note the operation of the circuit as a voltage-programmable 2-, 3-, or 4-valued oscillator.

http://ieeexplore.ieee.org/iel5/31/23595/01086230.pdf

Generation of noise by electronic iteration of the logistic map

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down ( 1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area. >

Mohamed I. Elmasry

Papers

Power reduction via an MTCMOS implementation of MOS current mode logic

Automatic synthesis of a multi-bus architecture for DSP

Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach

Generation of noise by electronic iteration of the logistic map

New full-voltage-swing BiCMOS buffers