Michael V. Aquilino

TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.

TL;DR: In this article, a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2 was demonstrated.

TL;DR: A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability in SOI CMOS 22nm technology.

TL;DR: A fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization, designed to enable both High Performance Compute (HPC) and mobile applications.

TL;DR: In this paper, a semiconductor substrate including a first epitaxial semiconductor layer is provided, and the first semiconductor material can be selected from materials more easily oxidized relative to the second material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.