Takashi Ando

TL;DR: High precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

TL;DR: In this article, a solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side, a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on first surface of the substrate, adjacent to the photodeter, the transfer gate transferring a signal charge accumulated in the photoder.

TL;DR: In this article, the authors leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) high-к/metal gate (HKMG) logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

TL;DR: In this article, a multilayer stack structure with at least one region and including a dielectric layer disposed over a substrate is provided, where a threshold voltage of the first region is independent of the threshold voltage in the second region.

TL;DR: In this paper, a case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric.