This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.

Cool Chips: Opportunities and Implications for Power and Thermal Management

The current conduction process through a nanowire wrap-around-gate, /spl sim/50 nm channel diameter, silicon MOSFET has been investigated and compared with a /spl sim/2 /spl mu/m wide slab, /spl sim/200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (/spl sim/3/spl times/) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to /spl sim/1200 cm/sup 2//V s compared to /spl sim/400 cm/sup 2//V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.

Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

Scaling silicon MOS devices to their limits

This paper proposes a probe-based force-controlled nanoindentation system employing a four-beam spring. The applied normal load is obtained by a force-modulation module with a four-beam spring and a capacitive displacement sensor, and the maximum normal force can be provided by this system is about 500 mN, which is determined by the precision approaching range of the probe in the vertical direction and the elastic yield strength of the four-beam spring. The closed-loop control accuracy of the normal force is about 0.3 mN. The penetration depth during the indentation process can be obtained by comparing the deflection of the four-beam spring with the elongation of the piezoelectric ceramic transducer (PZT). A rotating ring is utilized to control the orientation of the probe to broaden the machining diversity. The force-modulation module is set on a three-axes moving platform, and the relatively position between the probe and the sample surface can be controlled with a resolution of 1 nm in the horizontal plane, which indicates the high feeding accuracy between two adjacent indentations. Nanoindentation tests were performed using finite element (FE) simulation and experimental approaches with two typical indenters. In addition, 20 × 20 indentation arrays obtained by the probe rotation angles of 0° and 45° are also fabricated successfully. Based on these results, the feasibility of the developed system is verified for the probe-based force-controlled indentation-type micromachining.

A probe-based force-controlled nanoindentation system using an axisymmetric four-beam spring

We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon‐on‐insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal‐over‐gate structure. Mix‐and‐match lithography, including the use of electron‐beam lithography for all critical levels, x‐ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to fa...

Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor

In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.

Very high performance 50 nm CMOS at low temperature

A novel disposable polysilicon/RTCVD nitride sidewall process for sub-50 nm CMOS has been developed. This process allows the gate and deep source drain doping and anneals to be performed before the shallow extension and halo, thus enabling independent optimization of gate activation and low-thermal-cycle abrupt junctions. The new process offers much higher etch selectivities in terms of sidewall formation and strip operations than the oxide and nitride sidewall processes. In addition, it also gives much better sidewall dimensional control for device optimization. Sub-100 nm device fabricated with disposable sidewall process show less poly depletion (thinner Tinv) and significantly improved drive current than those fabricated with the conventional process. A high transconductance of 1150 mS/mm is obtained with the shortest device of 32 nm gate length generated by the new disposable polysilicon sidewall process.

R. A. Roy

Papers

Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor

Very high performance 50 nm CMOS at low temperature

New polysilicon disposable sidewall process for sub-50 nm CMOS