Christopher P. D'Emic

TL;DR: An overview of recent work on ultrathin (, 100 A) films of metal oxides deposited on silicon for advanced gate dielectrics applications is presented in this article, where the authors illustrate the 23 2 2 2 3 complex processing, integration and device related issues for high dielectric constant ('high-K') materials.

TL;DR: In this paper, a novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFETs on (100) surface) through wafer bonding and selective epitaxy devices with physical gate oxide thickness of 12 nm.

TL;DR: In this paper, growth behavior, structure, thermal stability and electrical properties of ultrathin hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl4 and H2O at 300°C on a bare silicon surface or a thin thermally grown SiO2-based interlayer.

TL;DR: In this article, the authors discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects for high-K dielectric integration into current Si technology.

TL;DR: In this article, the authors investigated the dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] with the equivalent gate dielectric thickness less than 3 nm.