K
K.-L. Lee
Researcher at IBM
Publications - 16
Citations - 545
K.-L. Lee is an academic researcher from IBM. The author has contributed to research in topics: Gate dielectric & Threshold voltage. The author has an hindex of 8, co-authored 16 publications receiving 451 citations.
Papers
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Proceedings ArticleDOI
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
J. Kedzierski,Edward J. Nowak,T. Kanarsky,Y. Zhang,Diane C. Boyd,Roy A. Carruthers,C. Cabral,R. Amos,Christian Lavoie,Ronnen Andrew Roy,J. Newbury,E. Sullivan,J. Benedict,P. Saunders,Keith Kwong Hon Wong,Donald F. Canaperi,Mahadevaiyer Krishnan,K.-L. Lee,Beth Ann Rainey,David M. Fried,Peter E. Cottrell,Hon-Sum P. Wong,Meikei Ieong,Wilfried Haensch +23 more
TL;DR: In this paper, metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation, and they satisfy the following metal gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on/I/sub off, and adjustable V/sub t/.
Journal ArticleDOI
Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources
Zhen Zhang,Francois Pagette,Christopher P. D'Emic,Bin Yang,Christian Lavoie,Yu Zhu,Marinus Hopstaken,Siegfried L. Maurer,Conal E. Murray,M. Guillorn,D. Klaus,J.J. Bucchignano,John Bruley,John A. Ott,A. Pyzyna,J. Newbury,W. Song,V Chhabra,G. Zuo,K.-L. Lee,Ahmet S. Ozcan,J. Silverman,Q.C. Ouyang,Dae-Gyu Park,Wilfried Haensch,Paul M. Solomon +25 more
TL;DR: In this article, an extremely low contact resistivity of 6-7 × 10-9 Ω·cm2 between Ni0.9Pt0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation.
Proceedings ArticleDOI
ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing
Jianshi Tang,Douglas M. Bishop,Seyoung Kim,Matthew Copel,Tayfun Gokmen,Teodor K. Todorov,Sanghoon Shin,K.-L. Lee,Paul M. Solomon,Kevin K. Chan,Wilfried Haensch,John Rozen +11 more
TL;DR: A nonvolatile Electro-Chemical Random-Access Memory (ECRAM) based on lithium (Li) ion intercalation in tungsten oxide (WO3) for high-speed, low-power neuromorphic computing is demonstrated.
Proceedings ArticleDOI
Metal-oxide based, CMOS-compatible ECRAM for Deep Learning Accelerator
Seyoung Kim,John A. Ott,Takashi Ando,Hiroyuki Miyazoe,Vijay Narayanan,John Rozen,Teodor K. Todorov,Murat Onen,Tayfun Gokmen,Douglas M. Bishop,Paul M. Solomon,K.-L. Lee,Matthew Copel,Damon B. Farmer +13 more
TL;DR: A CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing is demonstrated and a successful stochastic gradient descent algorithm demonstration in hardware is shown.
Proceedings ArticleDOI
Poly-Si/AlN/HfSiO Stack for Ideal Threshold Voltage and Mobility in Sub-100 nm MOSFETs
K.-L. Lee,Martin M. Frank,Vamsi Paruchuri,Eduard A. Cartier,Barry Linder,Nestor A. Bojarczuk,X. Wang,J. Rubino,Michelle L. Steen,P. Kozlowski,J. Newbury,E. Sikorski,Philip L. Flaitz,Michael A. Gribelyuk,Paul C. Jamison,G. Singco,Vijay Narayanan,Sufi Zafar,Supratik Guha,P. Oldiges,Rajarao Jammy,Meikei Ieong +21 more
TL;DR: In this paper, a scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (Vt) shifts.