Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

The miniaturization of components used in the construction of working devices is being pursued currently by the large-downward (top-down) fabrication. This approach, however, which obliges solid-state physicists and electronic engineers to manipulate progressively smaller and smaller pieces of matter, has its intrinsic limitations. An alternative approach is a small-upward (bottom-up) one, starting from the smallest compositions of matter that have distinct shapes and unique properties-namely molecules. In the context of this particular challenge, chemists have been extending the concept of a macroscopic machine to the molecular level. A molecular-level machine can be defined as an assembly of a distinct number of molecular components that are designed to perform machinelike movements (output) as a result of an appropriate external stimulation (input). In common with their macroscopic counterparts, a molecular machine is characterized by 1) the kind of energy input supplied to make it work, 2) the nature of the movements of its component parts, 3) the way in which its operation can be monitored and controlled, 4) the ability to make it repeat its operation in a cyclic fashion, 5) the timescale needed to complete a full cycle of movements, and 6) the purpose of its operation. Undoubtedly, the best energy inputs to make molecular machines work are photons or electrons. Indeed, with appropriately chosen photochemically and electrochemically driven reactions, it is possible to design and synthesize molecular machines that do work. Moreover, the dramatic increase in our fundamental understanding of self-assembly and self-organizational processes in chemical synthesis has aided and abetted the construction of artificial molecular machines through the development of new methods of noncovalent synthesis and the emergence of supramolecular assistance to covalent synthesis as a uniquely powerful synthetic tool. The aim of this review is to present a unified view of the field of molecular machines by focusing on past achievements, present limitations, and future perspectives. After analyzing a few important examples of natural molecular machines, the most significant developments in the field of artificial molecular machines are highlighted. The systems reviewed include 1) chemical rotors, 2) photochemically and electrochemically induced molecular (conformational) rearrangements, and 3) chemically, photochemically, and electrochemically controllable (co-conformational) motions in interlocked molecules (catenanes and rotaxanes), as well as in coordination and supramolecular complexes, including pseudorotaxanes. Artificial molecular machines based on biomolecules and interfacing artificial molecular machines with surfaces and solid supports are amongst some of the cutting-edge topics featured in this review. The extension of the concept of a machine to the molecular level is of interest not only for the sake of basic research, but also for the growth of nanoscience and the subsequent development of nanotechnology.

Artificial Molecular Machines.

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

The silicon-based microelectronics industry is rapidly approaching a point where device fabrication can no longer be simply scaled to progressively smaller sizes. Technological decisions must now be made that will substantially alter the directions along which silicon devices continue to develop. One such challenge is the need for higher permittivity dielectrics to replace silicon dioxide, the properties of which have hitherto been instrumental to the industry's success. Considerable efforts have already been made to develop replacement dielectrics for dynamic random-access memories. These developments serve to illustrate the magnitude of the now urgent problem of identifying alternatives to silicon dioxide for the gate dielectric in logic devices, such as the ubiquitous field-effect transistor.

Alternative dielectrics to silicon dioxide for memory and logic devices

We elucidate the atomic and electronic structure of graphene oxide (GO) using annular dark field imaging of single and multilayer sheets and electron energy loss spectroscopy for measuring the fine structure of C and O K-edges in a scanning transmission electron microscope. Partial density of states and electronic plasma excitations are also measured for these GO sheets showing unusual π* + σ* excitation at 19 eV. The results of this detailed analysis reveal that the GO is rough with an average surface roughness of 0.6 nm and the structure is predominantly amorphous due to distortions from sp3 C−O bonds. Around 40% sp3 bonding was found to be present in these sheets with measured O/C ratio of 1:5. These sp2 to sp3 bond modifications due to oxidation are also supported by ab initio calculations.

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Atomic and Electronic Structure of Graphene-Oxide

The narrowest feature on present-day integrated circuits is the gate oxide—the thin dielectric layer that forms the basis of field-effect device structures. Silicon dioxide is the dielectric of choice and, if present miniaturization trends continue, the projected oxide thickness by 2012 will be less than one nanometre, or about five silicon atoms across1. At least two of those five atoms will be at the silicon–oxide interfaces, and so will have very different electrical and optical properties from the desired bulk oxide, while constituting a significant fraction of the dielectric layer. Here we use electron-energy-loss spectroscopy in a scanning transmission electron microscope to measure the chemical composition and electronic structure, at the atomic scale, across gate oxides as thin as one nanometre. We are able to resolve the interfacial states that result from the spillover of the silicon conduction-band wavefunctions into the oxide. The spatial extent of these states places a fundamental limit of 0.7 nm (four silicon atoms across) on the thinnest usable silicon dioxide gate dielectric. And for present-day oxide growth techniques, interface roughness will raise this limit to 1.2 nm.

The electronic structure at the atomic scale of ultrathin gate oxides

Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current drive capability and transconductance We demonstrate that I/sub Dsat//spl ap/18 mA//spl mu/m can be achieved with a 60 nm gate at 15 V using a 13-14 nm gate oxide with a gate leakage current less than 20 nA//spl mu/m/sup 2/ Furthermore, we find that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this

Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak drive performance in an nMOSFET was observed at t/sub ox//spl ap/1.3 nm for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the peak performance in a pMOSFET was observed at t/sub ox//spl ap/1.5 nm for a -1.5 V supply with T/sub p//spl ap/0.5. Since the carrier scattering in the channel is due predominately to interface roughness, reducing the transverse surface field, either by reducing the gate voltage or by increasing the oxide thickness, can be used to improve the transmittance T/sub n//spl rarr/0.85, T/sub p//spl rarr/0.6, while diminishing the drive current.

The ballistic nano-transistor

Determining the cross-sectional doping profile of very small metal–oxide–semiconductor field effect transistors and specifically the direct measurement of their channel length is necessary for true channel engineering to be possible. Scanning capacitance microscopy (SCM) has generated unprecedented images of the cross-sectional doping profiles of very small transistors. The bias voltage dependence of these images has motivated us to investigate the SCM technique in greater detail. Using electrical simulations, we have focused on the pn junction to establish the qualitative and quantitative relationship between the bias voltage and the pn junction location. The ability to confidently interpret the images produced with SCM will allow us to improve simulation models, trouble-shoot process flow, and determine the effective channel length of semiconductor devices.

S. Moccio

Papers

The electronic structure at the atomic scale of ultrathin gate oxides

Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs

The ballistic nano-transistor

Quantification of scanning capacitance microscopy imaging of the pn junction through electrical simulation

Understanding the limits of ultrathin SiO 2 and Si-O-N gate dielectrics for sub-50 nm CMOS