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Shahin Nazarian

Researcher at University of Southern California

Publications -  127
Citations -  1854

Shahin Nazarian is an academic researcher from University of Southern California. The author has contributed to research in topics: Logic gate & Smart grid. The author has an hindex of 18, co-authored 121 publications receiving 1420 citations. Previous affiliations of Shahin Nazarian include Magma Design Automation.

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H₂O-Cloud: A Resource and Quality of Service-Aware Task Scheduling Framework for Warehouse-Scale Data Centers

TL;DR: The proposed H2O-Cloud is highly scalable and considers comprehensive information, such as various workload scenarios, cloud platform configurations, user request information, and dynamic pricing model, to improve resource usage effectiveness while maintaining quality of service (QoS).
Proceedings ArticleDOI

Sensitivity-based gate delay propagation in static timing analysis

TL;DR: The key contribution of the proposed methodology is to base the timing analysis on the sensitivity of the output waveform to the input waveform and accurately, yet efficiently, propagate equivalent electrical waveforms throughout a VLSI circuit.
Proceedings ArticleDOI

VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology

TL;DR: VeriSFQ as discussed by the authors is a semi-formal verification framework for single-flux quantum (SFQ) circuits using the Universal Verification Methodology (UVM) standard.
Proceedings ArticleDOI

Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradation

TL;DR: This paper addresses the coscheduling problem of HVAC control and battery management to achieve energy-efficient buildings, while also accounting for the degradation of the battery state-of-health during charging and discharging operations which determines the amortized cost of owning and utilizing a battery storage system.

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods Maximum chip performance under peak permissible temperature limits may be achieved with the help of combined electrical and thermal simulation of VLSI circuits.

TL;DR: In this article, the authors present a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power very large scale integration (VLSI) circuits.