Stéphane Adriaensen

TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.

TL;DR: Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, the authors demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under lowvoltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC.

TL;DR: In this paper, an engineering Lorentzian model has been validated and used in order to determine the SOI floating body effect related noise, continuously from fully-to partially-depleted regimes.

TL;DR: It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300/spl deg/C.

TL;DR: In this article, an ultra-low power (ULP) electronic circuit with a series connection of an n-MOS transistor and a mOS transistor, each having a source and a drain, is described.