Laurent Vancaillie

TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.

TL;DR: In this paper, the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters, are analyzed.

TL;DR: Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, the authors proposed to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage.

TL;DR: It is demonstrated how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components.

TL;DR: In this paper, the potential applicability of SOI MOS transistors with non-doped (or intrinsic) channels for analog applications is discussed, and the comparison of doped and intrinsic nMOSFETs in terms of parameters of the importance for analog designers is presented.