Z
Z. Tao
Researcher at Katholieke Universiteit Leuven
Publications - 21
Citations - 349
Z. Tao is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Metal gate & Layer (electronics). The author has an hindex of 6, co-authored 16 publications receiving 261 citations.
Papers
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Proceedings ArticleDOI
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Hans Mertens,Romain Ritzenthaler,Andriy Hikavyy,Min-Soo Kim,Z. Tao,Kurt Wostyn,S. A. Chew,A. De Keersgieter,G. Mannaert,Erik Rosseel,Tom Schram,Katia Devriendt,Diana Tsvetanova,Harold Dekkers,Steven Demuynck,Adrian Chasin,E. Van Besien,A. Dangol,S. Godny,Bastien Douhard,N. Bosman,O. Richard,J. Geypen,Hugo Bender,Kathy Barla,Dan Mocuta,Naoto Horiguchi,A. V-Y. Thean +27 more
TL;DR: In this paper, gate-all-around (GAA) n-and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs) were reported.
Proceedings ArticleDOI
Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS
Anabela Veloso,Geert Hellings,Moon Ju Cho,Eddy Simoen,Katia Devriendt,Vasile Paraschiv,E. Vecchio,Z. Tao,J. Versluijs,Laurent Souriau,Harold Dekkers,Stephan Brus,J. Geypen,P. Lagrain,Hugo Bender,Geert Eneman,Philippe Matagne,A. De Keersgieter,Wen Fang,Nadine Collaert,Aaron Thean +20 more
TL;DR: In this paper, a comprehensive evaluation of different device architectures from a device and circuit performance viewpoint: gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, both built using various doping schemes.
Proceedings ArticleDOI
Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect
Liesbeth Witters,Jerome Mitard,Roger Loo,Steven Demuynck,S. A. Chew,Tom Schram,Z. Tao,Andriy Hikavyy,Jianwu Sun,Alexey Milenin,Hans Mertens,Christa Vrancken,Paola Favia,Marc Schaekers,Hugo Bender,Naoto Horiguchi,Robert Langer,Kathy Barla,Dan Mocuta,Nadine Collaert,A. V-Y. Thean +20 more
TL;DR: In this paper, the authors integrated a strain relaxed SiGe p-channel FinFET on a high density 45nm Fin pitch using a replacement channel approach on Si substrate, and the I ON /I OFF benchmark showed that the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.
Proceedings ArticleDOI
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Anabela Veloso,Bertrand Parvais,Philippe Matagne,Eddy Simoen,T. Huynh-Bao,Vasile Paraschiv,E. Vecchio,Katia Devriendt,Erik Rosseel,M. Ercken,Boon Teik Chan,C. Delvaux,Efrain Altamirano-Sanchez,J. Versluijs,Z. Tao,Samuel Suhard,Stephan Brus,A. Sibaja-Hernandez,Niamh Waldron,P. Lagrain,O. Richard,Hugo Bender,Adrian Chasin,B. Kaczer,Tsvetan Ivanov,S. Ramesh,K. De Meyer,Julien Ryckaert,Nadine Collaert,Aaron Thean +29 more
TL;DR: In this article, the junctionless gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral configuration were compared to the conventional gate-and-allow mode (IM) GAA-NPNs, showing similar speed and voltage gain, and reduced LF noise.
Proceedings ArticleDOI
Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Anabela Veloso,T. Huynh-Bao,Erik Rosseel,Vasile Paraschiv,Katia Devriendt,E. Vecchio,C. Delvaux,Boon Teik Chan,M. Ercken,Z. Tao,W. Li,Efrain Altamirano-Sanchez,J. Versluijs,Stephan Brus,Philippe Matagne,Niamh Waldron,Julien Ryckaert,Dan Mocuta,Nadine Collaert +18 more
TL;DR: In this paper, the authors report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency.