G
G. Mannaert
Researcher at Katholieke Universiteit Leuven
Publications - 24
Citations - 657
G. Mannaert is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Metal gate & CMOS. The author has an hindex of 13, co-authored 24 publications receiving 480 citations.
Papers
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Proceedings ArticleDOI
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
Hans Mertens,Romain Ritzenthaler,Andriy Hikavyy,Min-Soo Kim,Z. Tao,Kurt Wostyn,S. A. Chew,A. De Keersgieter,G. Mannaert,Erik Rosseel,Tom Schram,Katia Devriendt,Diana Tsvetanova,Harold Dekkers,Steven Demuynck,Adrian Chasin,E. Van Besien,A. Dangol,S. Godny,Bastien Douhard,N. Bosman,O. Richard,J. Geypen,Hugo Bender,Kathy Barla,Dan Mocuta,Naoto Horiguchi,A. V-Y. Thean +27 more
TL;DR: In this paper, gate-all-around (GAA) n-and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs) were reported.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Hans Mertens,Romain Ritzenthaler,Adrian Chasin,Tom Schram,Eddy Kunnen,Andriy Hikavyy,Lars-Ake Ragnarsson,Harold Dekkers,T. Hopf,Kurt Wostyn,Katia Devriendt,S. A. Chew,Min-Soo Kim,Y. Kikuchi,Erik Rosseel,G. Mannaert,Stefan Kubicek,Steven Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,Hugo Bender,Kathy Barla,Naoto Horiguchi,Dan Mocuta +25 more
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Proceedings ArticleDOI
Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization
Romain Ritzenthaler,Hans Mertens,V. Peña,Gaetano Santoro,Adrian Chasin,K. Kenis,Katia Devriendt,G. Mannaert,H. Dekkers,A. Dangol,Lin Yongjing,Shiyu Sun,Zhebo Chen,M. Kim,J. Machillot,Jerome Mitard,Naomi Yoshida,Nam-Sung Kim,Dan Mocuta,Naoto Horiguchi +19 more
TL;DR: In this paper, vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs are integrated in a CMOS dual Work Function Metal Replacement Metal Gate (RMG) flow.
Proceedings ArticleDOI
Tall triple-gate devices with TiN/HfO/sub 2/ gate stack
Nadine Collaert,Marc Demand,Isabelle Ferain,Judit Lisoni,R. Singanamalla,Paul Zimmerman,Yong-Sik Yim,Tom Schram,G. Mannaert,M. Goodwin,J.C. Hooker,F. Neuilly,Myeong-Cheol Kim,K. De Meyer,S. De Gendt,Werner Boullart,M. Jurezak,Serge Biesemans +17 more
TL;DR: In this article, the performance of triple gate triple gate devices with a MOCVD TiN/HfO gate stack has been demonstrated for the first time, where the transistors have physical gate lengths down to 40 nm, and 60 nm tall and 10 nm wide fins.
Proceedings ArticleDOI
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
S. Subramanian,Maryamsadat Hosseini,Thomas Chiarella,S. Sarkar,P. Schuddinck,Boon Teik Chan,D. Radisic,G. Mannaert,Andriy Hikavyy,Erik Rosseel,Farid Sebaai,Antony Premkumar Peter,T. Hopf,P. Morin,S. Wang,Katia Devriendt,D. Batuk,G. T. Martinez,Anabela Veloso,E. Dentoni Litta,Sylvain Baudot,Yong Kong Siew,X. Zhou,B. Briggs,E. Capogreco,J. Hung,R. Koret,Alessio Spessot,Julien Ryckaert,Steven Demuynck,Naoto Horiguchi,Juergen Boemmels +31 more
TL;DR: This paper reports the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform and demonstrates functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices.