Juergen Boemmels

TL;DR: The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework and can eventually outperform the finFET device and meet the N3 targets in power and performance.

TL;DR: A novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling compared to FinFET and GAA devices.

TL;DR: This work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability, and suggests a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend.

TL;DR: This paper reports the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform and demonstrates functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices.

TL;DR: In this article, an alternative integration scheme based on the replacement of a sacrificial template by ultralow-k dielectric is studied, which solves the two major challenges in conventional Cu/low-k damascene integration approach: low k plasma damage and metal penetration during barrier deposition on porous materials.