Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The silicon-based microelectronics industry is rapidly approaching a point where device fabrication can no longer be simply scaled to progressively smaller sizes. Technological decisions must now be made that will substantially alter the directions along which silicon devices continue to develop. One such challenge is the need for higher permittivity dielectrics to replace silicon dioxide, the properties of which have hitherto been instrumental to the industry's success. Considerable efforts have already been made to develop replacement dielectrics for dynamic random-access memories. These developments serve to illustrate the magnitude of the now urgent problem of identifying alternatives to silicon dioxide for the gate dielectric in logic devices, such as the ubiquitous field-effect transistor.

Alternative dielectrics to silicon dioxide for memory and logic devices

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Dielectric breakdown mechanisms in gate oxides

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Soft breakdown of ultra-thin gate oxide layers

The current–voltage characteristics of metal-oxide-semiconductor capacitors with a 42 nm SiO2 gate oxide are investigated After the occurrence of soft breakdown, which is observed during constant current stress of the devices, the gate current is shown to behave like a power law of the applied gate voltage We propose that this power law behavior is due to the formation of a percolation path between the electrons traps generated in the SiO2 layer during current stress of the capacitor We describe a simple model which accounts for the current–voltage characteristics between two neighbor trapping sites, as well as a distribution of percolation thresholds in these (finite size) ultrathin SiO2 layers The prediction of the model is in fair agreement with the experimental results in a large voltage range, and leads to a better description of the data than previously reported models Furthermore, it is shown that this percolation model can also explain the temperature dependence of the gate current after the

Model for the current–voltage characteristics of ultrathin gate oxides after soft breakdown

In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate current and substrate current as a function of the gate voltage after SBD are stable and unique curves, but for smaller area devices both currents become lower and unstable. This difference can be explained by the different energy available for discharging in the SBD path. It is shown that the SBD detection strongly depends on the test structure area. In nMOSFET's for positive gate polarity, the large increase in the substrate current at the SBD moment is proposed as a sensitive SBD detector. Two level fluctuations in the gate current are investigated at different voltages and are explained by means of a model where electron capture-emission in the traps of the SBD path induces local field fluctuations causing variations in the tunneling rate across the oxide. In the substrate current directly correlated two-level fluctuations are observed.

On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers

The dielectric breakdown under constant current stressing of 4.2 nm SiO2 gate oxides is investigated. After soft breakdown, which corresponds to an anomalous increase of the stress-induced leakage current of metal–oxide–semiconductor capacitors, the current behaves like a power law of the applied gate voltage VG. After soft breakdown, charge is further injected into the SiO2 layer in order to extract the effective resistivity ρeff of the system as a function of the density of oxide traps D generated in the layer. It is found that ρeff behaves like a power law of (D−Dc) where Dc is the critical density of traps generated at soft breakdown. These results are in fair agreement with the predictions of the percolation theory of nonlinear conductor networks. Besides, the value of the critical exponent related to the resistivity is close to the one expected in two dimensions.

Soft breakdown in ultrathin gate oxides: Correlation with the percolation theory of nonlinear conductors

It is shown that the conventional interpretation of constant current Q/sub BD/ to evaluate the influence of process variations on the reliability of MOS structures can lead to erroneous conclusions. For a fixed thickness, the comparison of Q/sub BD/-distributions of all processes that affect the breakdown statistics becomes even meaningless. For ultra-thin oxides, the impact of different processing conditions requires constant gate voltage instead of constant current density Q/sub BD/-tests.

Tanya Nigam

Papers

Soft breakdown of ultra-thin gate oxide layers

Model for the current–voltage characteristics of ultrathin gate oxides after soft breakdown

On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers

Soft breakdown in ultrathin gate oxides: Correlation with the percolation theory of nonlinear conductors

Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?